On-the-fly memory testing and automatic generation of bitmaps

Details On-the-fly memory testing and automatic generation of bitmaps On-the-fly memory testing and automatic generation of bitmaps

1998-10-19

2003-04-15

Beausoleil, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S733000, C714S719000, C714S057000

Reexamination Certificate

active

06550023

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains generally to semiconductor memory testing, and more particularly to a method and apparatus for testing on-chip RAM and automatically generating a bitmap indicating cell failures.
BACKGROUND OF THE INVENTION
The semiconductor industry continues to yield integrated circuits (ICs) of increasing complexity. To provide increased functionality and performance, many IC's include on-chip memory. On-chip memory may take on a variety of forms, including read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), flash EPROM (which allow the contents of the memory to be erased and reprogrammed on the fly), and random access memory (RAM). ROM, including each variety of ROM, is generally implemented using non-volatile memory that retains its programmed contents even when the chip itself is powered down. RAM is typically implemented using volatile memory which, although does not retain its contents when powered down, tends to be faster and consumes less power.
The use of on-chip ROM, regardless of variety, allows more generalized functionality to be provided within a chip due to the ability to implement and execute a wide variety of functions through software (or, more specifically, firmware) encoded in the memory. Furthermore, the erasable/reprogrammable varieties of ROM allow the functionality of a chip to be altered simply by changing the contents of the memory.
RAM is typically used to temporarily store data used in the calculation of some larger functions. The use of on-chip RAM greatly enhances chip performance because having the memory located physically within the chip itself reduces the data access overhead, and therefore the data access times, which contributes to the improvement of functionality and performance of an integrated circuit.
The trend in integrated circuit reliability is to provide at least some basic testing that is automatically performed by the chip itself upon power up. This type of testing is often termed “built-in self test”, or simply “BIST”. The function of a BIST is generally to perform a variety of circuit tests that verify the correct functionality of the chip immediately upon power up and before enabling full functionality of the chip. One of the tests typically performed by BIST is on-chip memory testing. Memory testing itself may include a number of tests, each designed to detect memory memory defects (e.g., a stuck bit cell, or a defective word line that causes an entire row of bit cells to fail) in the on-chip memory. The conditions that are used to detect memory cell defects are a function of the supporting hardware and firmware. When these conditions discover a defect that causes one or more of the memory cells to fail, the locations of the cells that failed as a result of the defect are recorded in what is termed herein as a “bitmap”.
Prior art solutions for locating failed memory cells in order to generate a bitmap for an IC required data to be read from the memory and transferred outside of the chip, either via serial methods such as the boundary scan interface for digital ICs of the Joint Test Action Group (JTAG) IEEE 1149.1 standard protocol, or parallel methods such as Direct Access Testing, both of which are well-known in the art. Once available externally, each data bit read out from memory is compared with an expected value of the data bit to determine whether or not a failure has occurred. In order to search an entire memory for various kinds of defects, this procedure is performed multiple times across each memory address, and the locations of all failures in the memory are recorded to generate a bitmap.
Those skilled in the art will appreciate that the prior art methods consume a significant amount of time and involve significant equipment expense and design overhead. Transferring data off-chip is very time-consuming, especially when using serial scan methods and if a bitmap of the entire memory is desired. In addition, expensive IC testers or similar equipment must be used to collect the data and perform the comparison. Furthermore, engineering effort must be spent during the design phase to incorporate the circuits necessary to make the memory data accessible outside the chip. This effort can be considerable, especially if the solution involves making memory data available in real-time.
Accordingly, a need exists for a method and apparatus for allowing automatic on-chip generation of a bitmap that indicates the location of failing cells of an integrated circuit memory.
SUMMARY OF THE INVENTION
The present invention is a novel method and apparatus that makes it possible to detect and locate failing cells in an integrated circuit memory. In accordance with the design of the invention, data coming out of the on-chip memory is compared to its expected value while it is still on-chip. In the event of a comparison mismatch (or failure), the results of the comparison and its corresponding address in memory are stored in registers that may be scanned by external hardware and recorded in a bitmap or stored in another on-chip location for later retrieval.
In accordance with a preferred embodiment of the invention, data coming out of on-chip memory is compared to one of two programmable values stored respectively in a pair of respective expected data registers. The result of the compare is placed in a compare results register. Each comparator outputs a 0 if its inputs are the same and a 1 if its inputs are different. If all of the bits in the compare results register are 0, then the data read from memory is the same as the data in the selected expected data register. Conversely, a 1 in the compare results register indicates that memory data does not agree with the selected expected data register. The location of the 1 in the compare results register corresponds to the location of the incorrect memory bit. The outputs of each of the comparators are logically OR'ed together to generate a fault indicator that indicates whether a mismatch occurred in the currently output addressed word in memory. The fault indicator may be used to halt the memory test long enough to scan the contents of the compare results register and obtain the address in memory that resulted in the fault indication. Once the address and its corresponding comparison results are scanned out and recorded in a bitmap, the memory test may be resumed to continue the process until the entire memory has been tested. Upon completion of the memory test, a bitmap of the failed cells for the entire memory has been recorded. The use of two expected data registers are particularly advantageous when executing conventional March tests which systematically fill the memory with one of two alternating values.


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