On-die termination circuit, method of controlling the same,...

Details On-die termination circuit, method of controlling the same,... On-die termination circuit, method of controlling the same,...

2011-01-11

2011-01-11

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S040000, C326S113000, C365S189050, C365S233110

Reexamination Certificate

active

07868648

ABSTRACT:
An on-die termination (ODT) circuit may include an ODT synchronous buffer and/or an ODT gate. The ODT synchronous buffer may be configured to generate a synchronous ODT command from an external ODT command in synchronization with a first clock signal delay-locked to an external clock signal. The ODT gate may be configured to generate signals for controlling ODT based on a second clock signal delay-locked to the external clock signal and the synchronous ODT command. The synchronous ODT command may be generated in a disabled period of the second clock signal.

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Notice of Office Action dated Mar. 26, 2008 for corresponding Korean Application No. 10-2007-0019925.

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