Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-06-29
2001-09-04
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S734000, C324S1540PB
Reexamination Certificate
active
06286115
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to testing of integrated circuits, and more specifically to a method and apparatus that permits accessing of memory arrays embedded in the integrated circuits independent of any embedded logic arrays associated with the integrated circuits.
BACKGROUND OF THE INVENTION
FIG. 1
is a simplified block diagram of an integrated circuit
10
according to the prior art. The integrated circuit
10
includes an embedded memory device
12
, also known as a matrix memory device
12
, together with spare or redundant memory cells
12
′. The embedded memory device
12
is coupled through an internal bus
14
to an embedded logic array
16
that is also coupled to I/O circuitry
18
dedicated to the embedded logic array
16
. As used herein, the term “embedded,” as applied to circuitry contained on the integrated circuit
10
, refers to a circuit having one or more associated busses that are not normally directly accessible from outside of the integrated circuit
10
.
In operation, the I/O circuitry
18
couples control and data signals from external circuitry (not illustrated) to the embedded logic array
16
. The embedded logic array
16
operates on the data signals in accordance with the control signals and generates intermediate or final results. These results are coupled from the embedded logic array
16
through the internal bus
14
and are stored in the embedded memory device
12
. The embedded logic aray
16
recalls these results at a later time and uses them to generate output signals that are then coupled from the integrated circuit
10
to the external circuitry through the embedded logic array
16
and the I/O circuitry
18
. While the above-described arrangement provides great advantages in achieving high data transfer rates between the memory device
12
and the logic circuitry
16
, it only permits the embedded memory device
12
to be externally accessed through the embedded logic array
16
. In other words, unless the embedded logic array
16
is operational, the embedded memory device
12
cannot be easily accessed for purposes such as testing. Further, the embedded memory device
12
may only be tested with those tests that are pre-programmed into the embedded logic array
16
or through the I/O circuitry
18
of the embedded logic array
16
.
The internal bus
14
includes ‘N’ data lines, where N may be large, e.g., the internal bus
14
may be 64, 128, 256 or 512 bits wide or may be even wider. When the internal bus
14
is wide or very wide, it is impractical to provide I/O pads dedicated to each bit or data line of the internal bus
14
. Furthermore, if the I/O pads
24
are to be connected to externally accessible terminals, then buffers, electrostatic discharge protection and other circuitry (not illustrated) must be provided for each data line of the internal bus
14
. Yet this additional circuitry for each data line would consume unacceptably large portions of the integrated circuit
10
in order to provide external access to all of the data lines of the internal bus
14
.
In many applications, the embedded memory device
12
is formed prior to forming the embedded logic array
16
for several different reasons. Many memory circuits, such as the embedded memory device
12
, require smaller linewidths (i.e., minimum feature sizes) than are necessary for the embedded logic array
16
, in order for the embedded memory device
12
to provide data storage densities consistent with economical fabrication of the integrated circuit
10
. Also, the processing steps required to fabricate the embedded memory device
12
may be different than those required to fabricate the embedded logic array
16
. These reasons, particularly in combination, often favor fabricating the embedded memory device
12
prior to fabricating the embedded logic array
16
.
A typical embedded memory device
12
in an integrated circuit
10
includes at least one array of memory cells (not illustrated) arranged in rows and columns. Each memory cell must be tested to ensure that it is operating properly. In a typical prior art test method, data having a first binary value (e.g., a “1”) are written to and read from all memory cells in the arrays, and thereafter data having a second binary value (e.g., a “0”) are typically written to and read from the memory cells. The data written to the memory cells are known as “write” data, and the data read from the memory cells are known as “read” data. The read data are compared to a corresponding set of expect data. The expect data correspond to read data that would be provided by the integrated circuit
10
if its embedded memory device
12
was operating properly. A memory cell is considered to be defective when the read data and the corresponding expect data do not agree. As understood by one skilled in the art, other test data patterns may be utilized in testing the memory cells, such as an alternating bit pattern, e.g., 101010, . . . , written to the memory cells in each row of the memory device
12
.
Defective memory cells that are identified by testing are replaced with non-defective memory cells from rows or columns of spare or redundant memory cells
12
′. In one conventional method for replacing defective memory cells, fuses on the integrated circuit
10
are blown in a pattern corresponding to the addresses of defective memory cells. The pattern is then compared to incoming addresses to select the rows or columns of redundant memory cells
12
′ to replace rows or columns in the memory device
12
containing the defective memory cells.
However, it is desirable to be able to test the embedded memory device
12
before the embedded logic array
16
has been formed. When fabrication yields for the embedded memory device
12
are poor, or when fabrication yields decrease, it may be undesirable to fabricate the embedded logic array
16
and combine it with the memory device
12
prior to testing the memory device
12
. Further, discovering fabrication problems early in forming the integrated circuit
10
allows corrective steps to be taken early, reducing the number of integrated circuits
10
affected by a particular fabrication problem. Early detection of fabrication problems favors increased yields and reduced waste.
Accordingly, there is a need for an on-chip test circuit to permit testing of embedded memory devices in integrated circuits prior to fabrication of dedicated logic circuits for the integrated circuits.
SUMMARY OF THE INVENTION
In one aspect of the present invention, an integrated circuit includes an embedded memory device coupled to an internal bus having a first number of data lines, a multiplexer and an I/O port having a second number of data lines that is less than the first number of data lines. The multiplexer allows the I/O port to be coupled to a portion of the data lines of the internal bus and thus to at least a portion of the embedded memory device. As a result, the embedded memory device may be tested or repaired before an embedded logic function associated with dedicated I/O pins or pads is added to the integrated circuit. This promotes improved economic efficiency by allowing a manufacturer to cull integrated circuits that do not have acceptable fabrication yields prior to fabrication of the embedded logic array.
REFERENCES:
patent: 4969148 (1990-11-01), Nadeau-Dpstie et al.
patent: 5400343 (1995-03-01), Crittenden et al.
patent: 5553082 (1996-09-01), Connor et al.
patent: 5659508 (1997-08-01), Lamphier et al.
patent: 5659748 (1997-08-01), Kennedy
patent: 5787096 (1998-07-01), Roberts et al.
patent: 5936974 (1999-08-01), Roberts et al.
patent: 6085346 (2000-07-01), Lepejian et al.
Ayukawa et al., “An Access-Sequence Control Scheme to Enhance Random-Access Performance of Embedded DRAM's,”IEEE Journal of Solid-State Circuits, vol. 33(5): 800-806, May 1998.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Moise Emmanuel L.
LandOfFree
On-chip testing circuit and method for integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with On-chip testing circuit and method for integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and On-chip testing circuit and method for integrated circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2516097