Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1997-12-01
2000-12-19
Moise, Emmanuel L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
714733, 365201, G11C 2900, G01R 3128
Patent
active
061638625
ABSTRACT:
An on-chip test circuit for evaluating on-chip signals for a semiconductor memory chip includes an on-chip signal associated with a memory circuit on the chip; said on-chip signal having a signal characteristic to be evaluated; an input circuit for receiving an off-chip test signal; and a test circuit that compares said on-chip signal and said test signal.
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patent: 5841786 (1998-11-01), Keyes
patent: 5848016 (1998-12-01), Kwak
Adams R. Dean
Cooley Edmond S.
Hansen Patrick R.
Hogg William N.
International Business Machines - Corporation
Moise Emmanuel L.
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