On-chip test circuit for evaluating an on-chip signal using an e

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

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Details

714733, 365201, G11C 2900, G01R 3128

Patent

active

061638625

ABSTRACT:
An on-chip test circuit for evaluating on-chip signals for a semiconductor memory chip includes an on-chip signal associated with a memory circuit on the chip; said on-chip signal having a signal characteristic to be evaluated; an input circuit for receiving an off-chip test signal; and a test circuit that compares said on-chip signal and said test signal.

REFERENCES:
patent: 5121081 (1992-06-01), Hori
patent: 5166836 (1992-11-01), Choi
patent: 5229770 (1993-07-01), Nakajima
patent: 5535164 (1996-07-01), Adams et al.
patent: 5841786 (1998-11-01), Keyes
patent: 5848016 (1998-12-01), Kwak

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