Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2002-11-04
2004-10-26
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S034000, C326S087000
Reexamination Certificate
active
06809546
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly, to an on-chip terminator that terminates a transmission line in a semiconductor integrated circuit, and a circuit and method for controlling the on-chip terminator.
2. Description of the Related Art
In general, when a data signal is communicated at high speed between circuit devices, reflection of the data signal occurs if the devices are not impedance matched. Thus, an information signal exchange system requires a terminal resistor that terminates a bus for impedance matching. The terminal resistor suppresses the reflection of a received signal to raise the integrity of the signal transferred.
The terminal resistor may be located on the inside or outside of a semiconductor-integrated chip (hereinafter referred to as, “semiconductor chip”). The terminal resistor in a semiconductor chip is usually called an on-chip terminator, on-die terminator or active terminator.
To be effectively used in a semiconductor chip, the on-chip terminator needs to be appropriately controlled according to an operation mode of the semiconductor chip, taken in consideration of power consumption and signal integrity. In other words, the on-chip terminator should be controlled differently depending on whether the operation mode is an input mode, an output mode, or a power down mode.
However, in the prior art, there is no particular apparatus, such as a circuit, for controlling an on-chip terminator included in a semiconductor chip, and thus, the on-chip terminator is controlled only in response to a control signal input from the outside of the semiconductor chip. In the prior art, since there is no apparatus for controlling an on-chip terminator, the terminal resistor is always connected between an input/output node and terminal voltage VTERM and/or ground. Thus, a current path is formed between the terminal voltage VTERM and ground, causing unnecessary power consumption. Also, in this case, the level of an output signal is lower than normal. Thus, there is a need to appropriately turn on or off the on-chip terminator.
FIG. 1
is a circuit diagram of a semiconductor chip including an on-chip terminator
110
. The on-chip terminator
110
is controlled by a terminator driving signal TE input from the outside of the semiconductor chip.
The on-chip terminator
110
includes first and second terminal resistors R
1
and R
2
, and first and second switches S
11
and S
12
. When the first switch S
11
is turned on, the first terminal resistor R
1
is connected to the terminal voltage VTERM, and when the second switch S
12
is turned on, the second terminal resistor R
2
is connected to the grounding voltage. Here, the first and second switches S
11
and S
12
are turned on or off in response to the output terminator driving signal TE.
As shown in
FIG. 1
, since the on-chip terminator
110
is controlled in response to the terminator driving signal TE input from the outside of the semiconductor chip, control of the on-chip terminator
110
at a desired instant of time is not usually achieved. For instance, when data is transmitted from a first semiconductor chip to a second semiconductor chip, the first semiconductor chip sends the terminator-driving signal TE to the second semiconductor chip so as to operate an on-chip terminator in the second data chip. Next, after a predetermined time interval, the first semiconductor chip sends the data to the second semiconductor chip. Thereafter, the first semiconductor chip inactivates the terminator-driving signal TE in a predetermined time after the completion of transmission of the data.
Therefore, if the on-chip terminator
110
is controlled asynchronously with a signal input from the outside of the semiconductor chip, the time margin is required to start and complete transmission of data. In this regard, an on-chip terminator is not available in a semiconductor chip that operates at high speed. Also, a semiconductor chip having an on-chip terminator requires complicated circuitry so as to control the on-chip terminator by receiving an external signal and converting the signal into an internal signal.
For these reasons, a semiconductor chip having an on-chip terminator additionally requires a control circuit that turns on/off the on-chip terminator at a desired instant of time, using an external signal and/or an internal signal generated by the semiconductor chip, thereby reducing power consumption and enabling high-speed transmission of data. Hereinafter, a combination of such a control circuit and an on-chip terminator is called an “on-chip termination apparatus”.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides an on-chip termination apparatus and method that controls an on-chip terminator at a desired instant of time using a signal generated by a semiconductor chip, thereby increasing the efficiency of transmission of data and reducing time loss.
There is also provided a semiconductor integrated circuit including an output buffer for generating an output driver driving signal in response to output data and a predetermined output enable signal; an output driver for transmitting the output data to outside of the semiconductor integrated circuit in response to the output driver driving signal; an on-chip terminator having at least one terminal resistor; and a terminator control circuit for turning on or off the on-chip terminator in response to the output enable signal.
Preferably, the terminator control circuit turns off the on-chip terminator in response to an activation of the output enable signal, and turns on the on-chip terminator in response to an inactivation of the output enable signal.
Preferably, the terminator control circuit comprises a replica of the output buffer, which has the same delay time as the output buffer.
According to another embodiment of the invention, there is provided an on-chip termination apparatus installed in a semiconductor integrated circuit that has a data output circuit for outputting data to the outside of the semiconductor integrated circuit via a pad and a data input circuit for receiving data from the outside via the pad, the on-chip termination apparatus including an on-chip terminator including at least one terminal resistor that is electrically connected to the pad; and a terminator control circuit for turning on or off the on-chip terminator in response to an output enable signal that enables or disables the data output circuit.
Preferably, the terminator control circuit turns off the on-chip terminator in response to an activation of the output enable signal, and turns on the on-chip terminator in response to an inactivation of the output enable signal.
According to still another embodiment of the invention, there is provided a method for controlling an on-chip terminator in a semiconductor integrated circuit including the on-chip terminator that has at least one bi-directional data input/output unit, an output driver for transmitting output data to the outside of the semiconductor integrated circuit, and at least one terminal resistor. The method includes generating an output enable signal for enabling/disabling the output driver; and turning on or off the on-chip terminator in response to the output enable signal, wherein the on-chip terminator is turned off in response to an activation of the output enable signal and the on-chip terminator is turned on in response to an inactivation of the output enable signal.
REFERENCES:
patent: 5467455 (1995-11-01), Gay et al.
patent: 5831467 (1998-11-01), Leung et al.
patent: 6026456 (2000-02-01), Ilkbahar
patent: 00-021260 (2000-04-01), None
Jang Seong-jin
Song Ho-Young
F.Chau & Associates LLC
Samsung Electronics Co,. Ltd.
Tran Anh Q.
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