Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-05-02
2006-05-02
Perveen, Rehana (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S242000
Reexamination Certificate
active
07039750
ABSTRACT:
A system for communication on a chip. The system includes an on-chip communication bus including plural tracks, and a plurality of stations that couple a plurality of on-chip components to the on-chip communication bus, whereby the plurality of on-chip components use the tracks to communicate. Each station preferably includes an initiator that requests permission to transmit outgoing data over a track to another station and that transmits the outgoing data, an arbiter that evaluates requests from other stations and selects a track on which to receive incoming data, and a target that receives the incoming data. The initiator can be connected to a grant multiplexor for selecting a grant line, with the grant multiplexor further including plural smaller multiplexors distributed across the chip. Likewise, the arbiter can be connected to a track multiplexor for selecting a track, with the track multiplexor further including plural smaller multiplexors distributed across the chip. Each station also can include a source queue for queuing outgoing data and a destination queue for queuing incoming data. Preferably, the queues are first-in-first-out registers. The source queue and the destination queue can serve to separate a first clock domain for the on-chip communication bus from a second clock domain for one of the plurality of on-chip components. More than one of the plurality of on-chip components can be coupled to the on-chip communication bus through one of the stations.
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Regula Jack
Shaw Jhy-Ping
Simmons Ronald A.
Winward Curtis
Woodard Ralph
Knoll Clifford
Perveen Rehana
PLX Technology, Inc.
Swernofsky Law Group PC
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