On-chip reset circuitry and method

Details On-chip reset circuitry and method On-chip reset circuitry and method

2006-05-02

2006-05-02

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S401000, C713S500000

Reexamination Certificate

active

07039823

ABSTRACT:
An integrated circuit includes an external reset input, a clock input for receiving a clock signal and a reset signal sub-circuit including an internal reset output connected to other circuits of the integrated circuit. The reset signal sub-circuit immediately supplies an internal reset signal upon receipt of the external reset signal and ceases to supply the internal reset signal upon a next clock signal following ceasing to receive the external reset signal. This asynchronously forces combinational logic to a reset state upon receipt of the internal reset signal and synchronously forces sequential logic to a reset state upon receipt of a next clock signal.

REFERENCES:
patent: 3867613 (1975-02-01), Schoon
patent: 4161787 (1979-07-01), Groves et al.
patent: 6075392 (2000-06-01), Sandner
patent: 6108778 (2000-08-01), LaBerge
patent: 6259478 (2001-07-01), Hori
patent: 6308229 (2001-10-01), Masteller

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