On-chip pulse-width control circuit for SRAM memories

Details On-chip pulse-width control circuit for SRAM memories On-chip pulse-width control circuit for SRAM memories

1986-08-06

1988-09-06

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Precharge

365233, 307265, G11C 700

Patent

active

047697911

ABSTRACT:
The circuit provides one or several banks of capacitors, the capacitors in each bank being identical in size. A single fuse for each bank of capacitors controls the connection of the capacitors to a pulse-width-determining node on each of the ATD (address-transition-detect) pulse generators of the SRAM device. Depending on the position of the fuse in the circuit, the blowing of a single fuse can either add to the capacitance at the ATD nodes or substract from it. Thus the pulse-width of all ATD pulse generators can be adjusted shorter or longer simultaneously by blowing a single fuse only.

REFERENCES:
patent: 4069429 (1978-01-01), White et al.
patent: 4639615 (1987-01-01), Lee et al.
patent: 4687951 (1987-08-01), McElroy

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