On-chip packet-based interconnections using repeaters/routers

Details On-chip packet-based interconnections using repeaters/routers On-chip packet-based interconnections using repeaters/routers

2005-11-18

2009-06-02

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S013000, C703S014000

Reexamination Certificate

active

07543250

ABSTRACT:
In some embodiments, multiple functional blocks (agents) in a complex integrated circuit are connected to a physically-distant shared resource (e.g. a memory controller) through packet buses which do not depend on establishing clock-cycle sequenced handshakes. On-chip repeaters including one or more register stages are used to segment the agent-shared resource interconnects into multiple segments, each shorter than a single-clock-cycle pathlength. The interconnects of multiple closely-spaced agents can be routed to the shared resource through an on-chip router having a single routed connection to the shared resource, for reducing the floorplan space taken by interconnects. The packet-based communications protocols do not require redesigning the agents or memory controller to make protocol changes accounting for the clock cycles inserted by repeaters and/or routers. Each agent can include a port register for storing a corresponding port number of the shared resource, to facilitate the host-programmable assignment of agents to shared resource ports.

REFERENCES:
patent: 6520161 (2003-02-01), Hazama
patent: 6587912 (2003-07-01), Leddige et al.
patent: 6708248 (2004-03-01), Garrett et al.

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