On-chip ESD protection in dual voltage CMOS

Details On-chip ESD protection in dual voltage CMOS On-chip ESD protection in dual voltage CMOS

2000-01-26

2000-11-07

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438154, 438275, 438197, 438232, 257357, 257500, 257546, 257342, H01L 218238

Patent

active

061435945

ABSTRACT:
In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.

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