On-chip Cu interconnection using 1 to 5 nm thick metal cap

Details On-chip Cu interconnection using 1 to 5 nm thick metal cap On-chip Cu interconnection using 1 to 5 nm thick metal cap

2007-07-24

2007-07-24

Dang, Phuc T. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C438S622000

Reexamination Certificate

active

11037970

ABSTRACT:
Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increases the adhesion strength between the Cu and dielectric, and reduces interface diffusion of Cu. In addition, the thin cap layer further increases electromigration Cu lifetime and reduces the stress induced voiding. The selective elements can be directly deposited onto the Cu embedded within the under layer dielectric without causing an electric short circuit between the Cu lines. These chosen elements are based on their high negative reduction potentials with oxygen and water, and a low solubility in and formation of compounds with Cu.

REFERENCES:
patent: 6399496 (2002-06-01), Edelstein et al.
patent: 6479389 (2002-11-01), Tsai et al.

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