On-chip bus architectures with interconnected switch points,...

Details On-chip bus architectures with interconnected switch points,... On-chip bus architectures with interconnected switch points,...

2005-10-06

2011-11-01

Misiura, Brian (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S300000, C710S305000, C710S317000, C370S254000, C370S255000, C370S258000, C370S406000, C370S414000

Reexamination Certificate

active

08051238

ABSTRACT:
An on-chip bus includes a plurality of switch points including first and second switch points, a plurality of inter-switch links including at least one inter-switch link coupled between the first switch point and the second switch point and configured to communicate data between the first switch point and the second switch point, and a plurality of functional block cores including first and second functional block cores coupled directly to the first switch point and configured to communicate data through the first switch point. Data transmitted from the first functional block core to the second functional block cores may pass through the first switch point without traversing any of the plurality of inter-switch links. Methods for communicating data on an on-chip bus are also disclosed.

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Notice to Submit a Response for Korean Patent Application No. 10-2004-0080009 mailed on Mar. 13, 2006.

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