On-chip automatic procedures for memory testing

Details On-chip automatic procedures for memory testing On-chip automatic procedures for memory testing

1996-06-07

1997-10-07

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

36518509, 371 225, G11C 700, G11C 2900

Patent

active

056755465

ABSTRACT:
The on-chip endurance test (Autocycle) and the parametric characterization test (Auto VccMax/Min) of this invention save test time and hardware by performance automatically on the memory chip upon transmittal of a single command (CONTROL CODE) to the chip from the tester. The automated test procedures of this invention run faster because the on-chip tester requires fewer externally issued commands (CONTROL CODEs) and requires fewer external status checks. The procedures of this invention permit the external tester to have a smaller number of input/output pins (CONTROL), decreasing the cost of the external test hardware. Specifically, the endurance test (Autocycle), automatically cycles the memory chip through any combination of programming, erasing, and/or compaction operations until either a failure has been detected or the required number of the test cycles has been completed. The parametric characterization test (AutoVccMax/Min) determines automatically the maximum supply voltage and/or the minimum supply voltage for data operation of the memory chip. The endurance test (Autocycle) uses a microsequencer (MC) and an on-chip built-in-logic-block-observation (BILBO) register to check information in a control-read-only memory (CROM). Output data from the control-read-only memory is latched in a BILBO register enhanced for use as a counter for large count. During the endurance test (Autocycle), the microsequencer (MC), using enhanced counter, monitors the number of on-chip controlled endurance test cycles. During the parametric characterization test (AutoVccMax/Min), an on-chip digital-analog converter (DAC) causes stepped changes in the supply voltage (Vcc) furnished to both the data cells (10) and the reference cells (10) of the memory.

REFERENCES:
patent: 542248 (1895-09-01), Naruke et al.
patent: 5068827 (1991-11-01), Yamada et al.

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