Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-01-08
2008-01-08
Whitmore, Stacy (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C700S095000, C702S094000, C324S765010
Reexamination Certificate
active
11163009
ABSTRACT:
Dynamic offset determination for each of a plurality of measurement systems for matching the systems is disclosed. One embodiment uses an artifact which is periodically run across the measurement system to be matched. Inputs for each run include the current offsets and historical data for the entire fleet and the new test measurement for the current measurement system under test. Evaluation based on exponentially weighted moving average and median calculation techniques may result in a new, reset offset for one or more measurement systems. The reset offset(s) is then applied to product measurements to nullify any tool matching issues.
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Brendler Andrew C.
Chianese Danielle R.
Jankovsky Susan M.
Young Roger M.
Hoffman Warnick & D'Alessandro LLC
Jaklitsch Lisa U.
Whitmore Stacy
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