NVRAM memory cell architecture that integrates conventional...

Details NVRAM memory cell architecture that integrates conventional... NVRAM memory cell architecture that integrates conventional...

2007-01-16

2007-01-16

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S191000, C365S230080

Reexamination Certificate

active

11056901

ABSTRACT:
A nonvolatile SRAM array has an array of integrated nonvolatile SRAM circuits arranged in rows and columns on a substrate. Each of the integrated nonvolatile SRAM circuits includes an SRAM cell, a first and second nonvolatile memory element. The SRAM cell has a latched memory element in communication first and second nonvolatile memory elements to receive and permanently retain the digital signal from the latched memory element. A power detection circuit detects a power interruption and a power initiation and communicates the detection of the power interruption and power initiation to the plurality of integrated nonvolatile SRAM circuits. The SRAM cell, upon detection of the power interruption, transmits the digital signal to the first and second nonvolatile memory elements. The SRAM cell of each of the nonvolatile static random access memories upon detection of the power initiation, receives the digital signal from the first and second nonvolatile memory elements.

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