NVRAM cell using sharp tip for tunnel erase

Details NVRAM cell using sharp tip for tunnel erase NVRAM cell using sharp tip for tunnel erase

1998-06-08

2001-05-15

Crane, Sara (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S317000, C257S321000

Reexamination Certificate

active

06232633

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to an non-volatile random access memory (NVRAM) cell and a method for fabricating thereof, and more particularly, to an NVRAM cell that has a at least one sharp tip or spike extending into a source or drain of the NVRAM cell.
2. Discussion of the Prior Art
Smart cards and mobile applications require low power NVRAM cells, such as electrically erasable programmable read only memories (EEPROM), where their storage state, e.g., logic high or low, is retained after power is removed. Advanced complementary metal oxide semiconductor (CMOS) cells and processes have been aggressively scaled down to reduce cell size and power supply voltage requirements for reading and writing and erasing the NVRAM cells. Scaled NVRAM cells require high voltages for programming or erasing the NVRAM cells. The high voltages associated with programming and erasing the NVRAM cells incompatible with CMOS device scaling.
FIG. 1
shows a schematic of a typical NVRAM cell
100
, having a floating gate
110
, a control gate
120
and two drain/source terminals
105
and
115
. The terminal
105
is the bitline of the cell
100
, it may be connected to decode circuitry. For simplicity, hereinafter, the bitline B/L terminal
105
will be referred to as a drain, while the other terminal
115
will be referred to as a source.
Depending on voltages applied to the bitline B/L terminal
105
, the control gate
120
and the source
115
, the floating gate
110
is charged (written) or discharged (erased). The discharge occurs only through the source terminal
115
. A floating gate
110
of the NVRAM cell
100
stores charges.
The floating gate
110
is covered by a dielectric insulating layer
130
, such as an oxy-nitride-oxide (ONO) layer, which is a combination of oxide, nitride, and reoxidation of the nitride, in order to retain the stored charges after the completion of writing or erasing operations. The dielectric insulating layer
135
located between the floating gate and the underlying substrate
140
is referred to as a tunnel oxide, which is normally thin to allow electron tunneling between the floating gate and the source (or the drain) of the floating gate transistor
100
.
The present disclosure relates to a stacked gate nonvolatile memory cell, where the signal is stored on the floating gate. Those skilled in the art will recognize that these cells can be operated in a number of ways. Two of the best methods used for cell operation are described below. These methods are not intended to be an exhaustive list, however, the practitioners of the art will recognize that they define two major classes for which other operation modes will derive.
Channel Hot Electron Write
To write the cell
100
in the Channel Hot Electron mode of operation, voltages are applied to the source
115
, the drain
105
, and the control gate
120
to turn on the channel region
125
. In this mode the current through the channel
125
generates hot electrons near the drain region
105
. Some small fraction of these hot electrons have enough energy to be injected into the floating gate
110
across the dielectric film
135
separating the floating gate
110
from the channel region
125
and the source
115
and the drain
105
regions. This dielectric film is typically silicon dioxide and is referred to as the tunnel oxide.
A typical set of voltages for an NFET memory cell is putting the source
115
to ground potential 0 volts, placing the drain
105
at a positive voltage typically e.g., 5 volts and placing a high potential on the control gate
120
e.g., 10 volts. The voltage on the floating gate
110
defines the conduction of the conduction region. The floating gate
110
is analogous to the gate on a standard CMOS transistor. However, since it is electrically isolated, the voltage applied to the control gate
120
is coupled to the floating gate
110
via a ratio of capacitance between the inter-gate dielectric
130
and the tunnel oxide
135
, and the bias conditions of the adjacent regions.
Tunnel Write
Writing the cell
100
using Tunnel Write mode of operation involves biasing the drain region
105
and the control gate
120
in such a manner as to create an electric field in the region of the tunnel oxide between the drain
105
and the floating gate
110
, such that electrons will tunnel from the drain region to the floating gate. In the example of the NFET memory cell
100
, the drain region
105
could be set at ground 0 volts, the source region
115
could be set at 5 volts, while the control gate
120
is biased to a high voltage e.g., 15 volts. As was the case with Channel Hot Electron mode of operation, the actual voltage on the floating gate
110
is defined by capacitive coupling between the floating gate
110
and all adjacent regions. Note that the currents required to Tunnel are much less than those required to inject electrons by Channel Hot Electrons.
Tunnel Erase
The erase operation is identical in the Channel Hot Electron Write mode and in the Tunnel Write mode of operation. To erase the cell
100
, the source region
115
is biased to a relatively high potential, and the control gate
120
is biased to a negative potential such that high electric field is produced across the tunnel oxide which will allow tunneling of electrons from the floating gate
110
to the source
115
. For example, in a NFET memory cell
100
the source
115
may be biased to 8 volts while the control gate
120
is biased to negative 6 volts.
As was the case during the Tunnel Write, the voltage on the floating gate
110
defines the field across the tunnel oxide. Since floating gate
110
is electrically isolated, the voltage is defined by capacitance ratios between the inter-gate dielectric and the tunnel oxide considering the voltages applied to the adjacent regions, i.e., the source
115
, the drain
105
, and the channel
125
. Writing the cell is an act of adding electrons to the floating gate
110
, while erasing the cell is an act of removing electrons from the floating gate
110
. It may also be shown that channel region
125
is conductive in the case of an erased NFET cell, while it does not conduct current readily in the written state.
One method to reduce the high NVRAM programming voltages is scaling or reducing the thickness of the tunnel oxide
135
located between a floating gate
110
and the source
115
. However, thin tunnel oxides have been associated with the loss of the stored charge on the floating gate
110
, so called retention fails. Thus, such cell cannot be used as non-volatile memory. Accordingly, there is a need to provide an NVRAM cell that operates properly at low voltages, without further reducing the thickness of the tunnel oxide and thus, avoiding problems associated with thinner tunnel oxide layers.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a non-volatile random access memory (NVRAM) cell that operates at low voltages, and a method making thereof, that eliminate the problems of conventional NVRAM cells.
Another object of the present invention is to provide an NVRAM cell with increased carrier tunneling without reducing the thickness of the tunnel oxide.
Yet another object of the present invention is to provide an NVRAM cell with high electric field regions that facilitate carrier tunneling for writing and/or erasing of charges stored on the floating gate.
These and other objects of the present invention are achieved by a non-volatile random access memory (NVRAM) cell that includes a substrate having source and drain regions. A spike, having a tip, extends in one of the source or the drain regions, or both and a spike tip extending from the drain region toward the floating gate. The spike facilitates tunneling of charges between the floating gate and the source region. In particular, in the embodiment of the present invention where the spike tip that extends from the floating gate into the source region provides a high electric field that facilitates tunneling of charge carriers

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