NROM cell with N-less channel

Details NROM cell with N-less channel NROM cell with N-less channel

2002-02-27

2004-06-15

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S954000

Reexamination Certificate

active

06750103

ABSTRACT:

BACKGROUND
The present invention relates generally to methods of fabrication of nitride read only memory (NROM) cells and arrays.
FIG. 1
illustrates a typical NROM cell. This cell includes a substrate
10
in which are implanted a bit line source
12
and drain
14
and on which lies an oxide-nitride-oxide (ONO) structure
16
having a layer of nitride
17
sandwiched between a lower oxide layer
18
and an upper oxide layer
20
. On the ONO structure
16
lies a polysilicon connecting block
26
, which functions as a gate conductor. On the source
12
and drain
14
are isolated oxide areas
62
, which function as insulators. Between the source
12
and drain
14
is a channel
15
under the ONO structure
16
.
The nitride section
17
provides the charge retention mechanism for programming the memory cell. Specifically, when programming voltages are provided to the source
12
, drain
14
and gate conductor
26
, electrons flow towards the drain
14
. According to the hot electron injection phenomenon, some hot electrons penetrate through the lower section of silicon oxide
18
, especially if the section
18
is thin, and are then collected in the nitride section
17
. As is known in the art, the nitride section
17
retains the received charge, labeled
24
, in a concentrated area adjacent the drain
14
. The concentrated charge
24
significantly raises the threshold of the portion of the channel of die memory cell under the charge
24
to be higher than the threshold of the remaining portion of the channel
15
.
When concentrated charge
24
is present (i.e. the cell is programmed), the raised threshold of the cell does not permit the cell to be placed into a conductive state during reading of the cell. If concentrated charge
24
is not present, the read voltage on gate conductor
22
can overcome the much lower threshold and accordingly, channel
15
becomes inverted and hence, conductive. It is noted that the threshold voltage V
th
of NROM cells is generally very sensitive to the voltages V
drain
and V
gate
provided on the drain
14
and on the gate conductor
26
, respectively.
FIGS. 2-5
illustrate a conventional approach to forming the NROM cell of FIG.
1
. The process begins by thermally growing a lower layer of silicon oxide
18
on a P-type silicon substrate
10
. Then, a silicon nitride layer
17
is deposited by LPCVD and the wafer is steam-sealed to form the upper silicon oxide layer
20
. Next, a doped layer of polysilicon is deposited over the wafer to a depth of about 4,000 angstroms. The polysilicon layer is patterned to form polysilicon connecting blocks
26
, with openings
30
in between.
A heavy dosage of arsenic
36
is then implanted into the wafer to form heavily doped, N-type, bit line areas
38
. The polysilicon connecting blocks
26
are used for connecting to conductive word lines which are common to other similar memory cells in the rows. Also, the polysilicon connecting blocks
26
function as masks to prevent the arsenic implant from reaching the underlying channel areas
15
.
The wafer is then subjected to an etch for removing portions of the oxide-nitride-oxide layers
18
,
17
, and
20
which are not covered by the polysilicon connecting blocks
26
. The remaining oxide-nitride-oxide layers
18
,
17
, and
20
are self-aligned with respect to the side edges of the overlying polysilicon connecting blocks
26
, as illustrated in FIG.
2
.
The process continues with the deposition of a layer of conformal silicon oxide
52
, such as tetra-ethoxysilane (TEOS), over the surface of the wafer to a depth of about 5,000 angstroms. A layer of photoresist
54
is then spun over the surface of the wafer for filling the contoured surface of the conformal silicon oxide layer
52
, and for providing a flat top surface. The wafer may be heated to a temperature effective to anneal the implant and activate the impurities to form diffused bit line regions
56
, shown in FIG.
3
. The diffused bit line regions
56
are elongate and are associated with other cells in the columns of the memory array.
An etching process is then employed for etching the photoresist
54
and the conformal silicon oxide layer
52
at the same rate. When such an etch is conducted, the removal of material proceeds uniformly downwardly, until the polysilicon connecting blocks
26
are reached. The top surface of the polysilicon connecting blocks
26
are planarized with respect to the top surface of the conformal silicon oxide layer
52
, forming isolated oxide areas
62
. The result is a planarized surface of the memory array, illustrated in FIG.
4
.
Finally, a second layer of doped polysilicon
68
is deposited over the surface of the wafer, as shown in
FIG. 5
, and patterned to define a word line extending in common with a number of other memory cells of the row. Importantly, the polysilicon word line
68
is in electrical contact with the first polysilicon layer forming the conductive connecting blocks
26
. Thus, when an address signal is applied to the word line
68
, such signal is applied simultaneously to the polysilicon connecting blocks
26
which function as gate conductors. All memory cells connected to the word line
68
which are not programmed with a concentrated charge on the silicon nitride layer
17
will conduct and present a low impedance between the associated pair of bit lines. Those memory cells in the row which are programmed so as to have a concentrated charge on the silicon nitride layer
17
will not be made conductive and thus will present a high impedance between the associated bit lines.
BRIEF SUMMARY
In one aspect, the present invention is an electrically programmable read-only memory device including an array of single transistor memory cells where each of said cells is read, programmed, and erased through a pair of associated bit lines and a single associated word line. The memory device is formed on a substrate. Each memory cell comprises a pair of bit lines extending in a first direction across the substrate, a pair of bit line dielectrics overlaying and covering the pair of bit lines, a charge-trapping layer formed over the channel region between the pair of bit lines, and a conductive connecting block formed on the charge-trapping layer. The charge-trapping layer comprises two oxide-nitride-oxide (ONO) structures separated by a gate oxide layer, where each ONO structures comprises a layer of nitride sandwiched between a bottom oxide layer and a top oxide layer. A plurality of straight, parallel-edge-word lines extend across the substrate in a second direction and cross over the bit lines and channel regions. Each word line comprises a conductive material and is separated from the substrate by the conductive connecting blocks and bit line dielectrics.
In a second aspect, the present invention concerns a first method of fabricating a nitride read only memory (NROM) chip. The method comprises creating an oxide-conductive layer on a substrate, where the oxide-conductive layer is formed of a first conductive layer on top of a thick oxide layer, laying down a bit line mask of photoresist generally in columns at least within a memory portion of the chip; removing at least a portion of the oxide-conductive layer wherever the photoresist is not present to form oxide-conductive-layer columns; implanting bit lines wherever the photoresist is not present and generally in columns; removing the photoresist; removing a portion of the remaining thick oxide layer from the oxide-conductive-layer columns to produce a recess; growing a thin oxide layer over the memory portion of the chip; depositing a nitride layer over the thin oxide layer to a thickness sufficient to fill the recess; removing the nitride layer except in the region or the recess; forming bit line dielectrics on top of the bit lines; and forming rows of a second conductive layer perpendicular to and on top of the bit line dielectrics and oxide-conductive-layer columns.
In a third aspect, the present invention concerns a second method of fabricating a nitride read only memory (NROM) chip. The

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