NROM cell with generally decoupled primary and secondary...

Details NROM cell with generally decoupled primary and secondary... NROM cell with generally decoupled primary and secondary...

2000-03-06

2002-08-06

Zarablan, Amir (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S261000, C365S185030, C365S185150, C365S185290, C257S315000

Reexamination Certificate

active

06429063

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to FLASH, electrically erasable, programmable read only memory (EEPROM) and nitride, programmable read only memory (NROM) cells in general and to secondary injection therein in particular.
BACKGROUND OF THE INVENTION
Floating gate memory cells are used for electrically erasable, programmable read only memory (EEPROM) and Flash EEPROM cells. As shown in
FIG. 1
to which reference is now made, floating gate cells comprise source and drain portions
102
and
104
embedded in a substrate
105
, between which is a channel
100
. A floating gate
101
is located above but insulated from channel
100
and a gate
112
is located above but insulated from floating gate
101
.
For most floating gate cells, the standard electron injection mechanism (for programming) is channel hot electron injection, in which the source to drain potential drop creates lateral field that accelerates channel electrons e
1
from source
102
to drain
104
. This is indicated by arrow
10
. Near drain
104
, a vertical field created by the gate voltage allows hot channel electrons e
1
to be injected (arrow
12
) into floating gate
101
.
There is another injection mechanism, known as “secondary electron injection”. As indicated by arrow
14
, some of the channel electrons e
1
create hole and electron pairs through ionization of valence electrons in channel
100
or drain
104
. The probability of the ionization is labeled M
1
and it indicates the ratio between the channel current and the hole substrate current.
Due to the positive potential of drain
104
, generated electron e
2
is collected (arrow
16
) by drain
104
. However, as indicated by arrow
18
, hole h
2
accelerates towards the low substrate potential of substrate
105
. On the way, another impact ionization event may occur, creating another electron-hole pair e
3
-h
3
, with probability M
2
. Hole h
3
is pulled (arrow
20
) further into substrate
105
and is of no concern. However, electron e
3
(known as the “secondary electron”) is accelerated (arrow
22
) toward positive gate
112
where, if it has gained sufficient energy, it is injected into floating gate
101
. The probability of this occurring is labeled T.
The current for secondary injection is defined as:
I
g
=I
ds
*M
1
*M
2
*T
where I
ds
is the channel current from source to drain.
Because this current is significant, some floating gate devices have been built to enhance it, thereby reducing programming time and programming voltages. The following articles discuss some possible methods to enhance the secondary injection:
J. D. Bude, et al., “Secondary Electron Flash—a High Performance, Low Power Flash Technology for 0.35 &mgr;m and Below”, IEDM 97, pp. 279-282;
J. D. Bude, et al., “EEPROM/Flash Sub 3.0V Drain-Source Bias Hot Carrier Writing”, IEDM 95, pp. 989-992; and
J. D. Bude and M. R. Pinto, “Modeling Nonequilibrium Hot Carrier Device Effects”,
Conference of Insulator Specialists of Europe
, Sweden, June 1997. These references enhance the secondary generation and injection in two ways as shown in
FIGS. 2A and 2B
to which reference is now made, by implanting (
FIG. 2A
) substrate
105
with Boron pockets
116
and by applying a negative substrate bias V
B
to substrate
105
(FIG.
2
B).
Boron pockets
116
(FIG.
2
A), when implanted with relatively high energy, enhance the field in the substrate and hence, enhance the probability M
2
of secondary generation. This higher Boron concentration is effective also in accelerating secondary electrons and hence, enhances their probability T of injection.
The potential drop V
db
from drain
104
to substrate
105
is larger by 1V than the potential drop V
ds
from drain to source due the built-in potential in the n+/p− substrate junction. This enhances both the probability M
2
of a secondary impact and the probability T of injection. To further enhance secondary injection, a negative substrate bias V
B
can be applied, as shown in FIG.
2
B.
It will be appreciated that the energy balance for secondary injection is a function of the drain voltage V
d
(which defines the voltage in the channel), the built-in potential V
bi
, the substrate voltage V
sub
and the energy De
sec
after impact ionization. This compares to the primary electron injection mechanism (of channel hot electron injection) which is a function of the drain to source voltage V
ds
.
Typically, if the drain to source voltage V
ds
is of 3V and the substrate voltage is at 0V, the primary electrons are accelerated by 3V while the secondary electrons are accelerated by 4V. If the substrate voltage is decreased to −1V, then the secondary electrons are accelerated by 5V. Thus, applying negative voltage to the substrate increases the secondary injection mechanism. This is illustrated in
FIG. 2B
which shows the potential energy across channel
100
(from drain
104
(at point A) to source
102
(point B) and into the substrate
105
(point C is at the electrode of substrate voltage V
b
). In
FIG. 2B
, the drain/source voltage V
ds
is 3V, the gate/source voltage V
gs
is 2V and the channel length is 0.25 &mgr;m.
The solid line, labeled
120
, indicates the potential energy in a standard situation where source/substrate voltage V
bs
is 0.0V. The potential energy drops from drain
104
to source
102
and then increases into substrate
105
. Thus, the total potential drop from drain (point A) to substrate (point C) is about 1 eV higher than that of the drain to source (point A to point B). A generated hole h
2
will escape the drain
104
and will create a secondary electron e
3
with energy of about 0.2-0.7 eV.
This energy, when combined with the acceleration of secondary electron e
3
over several volts of substrate to channel potential towards gate
112
, makes the probability of injection T of secondary electron e
3
higher than that of primary electron e
1
. However, there are many more primary electrons e
1
available than secondary electrons e
3
and thus, most of the injection remains the primary electrons e
1
. Since the injected electrons (primary and secondary) spread out in floating gate
101
, there is no way to tell where injection occurred.
When the source/substrate voltage V
bs
is decreased to −1.0V, shown with the dashed line
122
, the potential energy into substrate
105
increases, although the potential energy in the drain and across the channel does not change. The increased substrate potential provides additional energy to secondary electrons e
3
while not affecting the energy of channel electrons e
1
.
Secondary injection adds to the primary injection mechanism to provide a faster and/or lower voltage injection into a floating gate cell. Unfortunately, secondary injection is not good for all types of cells. There are some cells, such as nitride, programmable read only memory (NROM) cells, for which enhancing secondary injection appears not to enhance the operation of the cell.
NROM cells are described in Applicant's copending U.S. patent application Ser. No. 08/905,286, entitled “Two Bit Non-Volatile Electrically Erasable And Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping” which was filed Aug. 1, 1997. The disclosure of the above-identified application is incorporated herein by reference.
FIGS. 3A
,
3
B and
3
C, to which reference is now made, schematically illustrate the dual bit NROM cell. Similar to the floating gate cell of
FIG. 1
, the NROM cell has channel
100
between two bit lines
102
and
104
but, unlike the floating gate cell, the NROM cell has two separated and separately chargeable areas
106
and
108
. Each area defines one bit. For the dual bit cell of
FIGS. 3
, the separately chargeable areas
106
and
108
are found within a nitride layer
110
formed in an oxide-nitride-oxide (ONO) sandwich (layers
109
,
110
and
111
) underneath gate
112
.
To read the left bit, stored in area
106
, right bit line
104
is the drain and left bit line
102
is the source. This is known as the “read through” di

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