NRAM bit selectable two-device nanotube array

Details NRAM bit selectable two-device nanotube array NRAM bit selectable two-device nanotube array

2005-09-13

2005-09-13

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Systems using particular element

Semiconductive

C365S163000, C257S415000

Reexamination Certificate

active

06944054

ABSTRACT:
A non-volatile memory array includes a plurality of memory cells, each cell receiving a bit line, word line, and release line. Each memory cell includes a cell selection transistor and a restore transistor with first, second and third nodes. Each cell further includes an electromechanically deflectable switch, the position of which manifests the logical state of the cell. Each cell is bit selectable for read and write operations.

REFERENCES:
patent: 6128214 (2000-10-01), Kuekes et al.
patent: 6159620 (2000-12-01), Heath et al.
patent: 6183714 (2001-02-01), Smalley et al.
patent: 6198655 (2001-03-01), Heath et al.
patent: 6221330 (2001-04-01), Moy et al.
patent: 6232706 (2001-05-01), Dai et al.
patent: 6445006 (2002-09-01), Brandes et al.
patent: 6518156 (2003-02-01), Chen et al.
patent: 6548841 (2003-04-01), Frazier et al.
patent: 6559468 (2003-05-01), Kuekes et al.
patent: 6574130 (2003-06-01), Segal et al.
patent: 6586787 (2003-07-01), Shih et al.
patent: 6643165 (2003-11-01), Segal et al.
patent: 6673424 (2004-01-01), Lindsay et al.
patent: 6706402 (2004-03-01), Rueckes et al.
patent: 6750471 (2004-06-01), Bethune et al.
patent: 6759693 (2004-07-01), Vogeli et al.
patent: 6774052 (2004-08-01), Vogeli et al.
patent: 6781166 (2004-08-01), Lieber et al.
patent: 6784028 (2004-08-01), Rueckes et al.
patent: 6803840 (2004-10-01), Hunt et al.
patent: 6809465 (2004-10-01), Jin
patent: 2002/0130311 (2002-09-01), Lieber et al.
patent: 2002/0130353 (2002-09-01), Lieber et al.
patent: 2002/0172963 (2002-11-01), Kelley et al.
patent: 2002/0179434 (2002-12-01), Dai et al.
patent: 2003/0021966 (2003-01-01), Segal et al.
patent: 2003/0124325 (2003-07-01), Rueckes et al.
patent: 2003/0165074 (2003-09-01), Segal et al.
patent: 2003/0206436 (2003-11-01), Eaton et al.
patent: 2003/0234407 (2003-12-01), Vogeli et al.
patent: 2003/0236000 (2003-12-01), Vogeli et al.
patent: 2004/0085805 (2004-05-01), Segal et al.
patent: 2004/0159833 (2004-08-01), Rueckes et al.
patent: 2004/0164289 (2004-08-01), Rueckes et al.
patent: 2004/0175856 (2004-09-01), Jaiprakash et al.
patent: 2004/0181630 (2004-09-01), Jaiprakash et al.
patent: 2004/0191978 (2004-09-01), Rueckes et al.
patent: 2004/0214366 (2004-10-01), Segal et al.
patent: 2004/0214367 (2004-10-01), Segal et al.
patent: 2005/0041466 (2005-02-01), Rueckes et al.
patent: 2005/0047244 (2005-03-01), Rueckes et al.
patent: 2005/0056877 (2005-03-01), Rueckes et al.
patent: WO 01/03208 (2001-01-01), None
patent: WO 01/44796 (2001-06-01), None
patent: WO 04/065657 (2004-08-01), None
Ajayan, P.M., et al., “Nanometre-size tubes of carbon.”Rep. Prog. Phys., 1997, vol. 60, 1025-1062.
Ami, S. et al., “Logic gates and memory cells based on single C60electromechanical transistors.”Nanotechnology, 2001, vol. 12, 44-52.
Avouris, P., “Carbon nanotube electronics,”Chem. Physics, 2002, vol. 281, pp. 429-445.
Casavant, M.J. et al., “Neat macroscopic membranes of aligned carbon nanotubes,”Journal of Appl. Phys., 2003, vol. 93(4) 2153-2156.
Choi, W. B. et al., “Carbon-nanotube-based nonvolatile memory with oxide-nitride-film and nanoscale channel.”Appl. Phys. Lett., 2003, vol. 82(2) 275-277.
Cui, J.B. et al., “Carbon Nanotube Memory Devices of High Charge Storage Stability.”Appl. Phys. Lett., 2002, vol. 81(17) 3260-3262.
Dai, H. et al., “Controlled Chemical Routes to Nanotube Architectures, Physics, and Devices.”J. Phys. Chem . B, 1999, vol. 103, 111246-11255.
Dehon, A., “Array-Based Architecture for FET-Based, Nanoscale Electronics.”IEEE Transactions on Nanotechnology, 2003, vol. 2(1) 23-32.
Dequesnes, M. et al., “Calculation of pull-in voltages for carbon-nanotube-based nanoelectromechanical switches.”Nanotechnology, 2002, vol. 13, 120-131.
Dequesnes, M. et al., “Simulation of carbon nanotube-based nanoelectromechanical switches.”Computational Nanoscience and Nanotechnology, 2002, 383-386.
Fan, S. et al., “Carbon nanotube arrays on silicon substrates and their possible application.”Physica E, 2000, vol. 8, 179-183.
Farajian, A. A. et al., “Electronic transport through bent carbon nanotubes: Nanoelectromechanical sensors and switches.”Phys. Rev. B, 2003, vol. 67, 205423-1-205423-6.
Fischer, J.E. et al., “Magnetically aligned single wall carbon nanotube films: Preferred orientation and anisotropic transport properties.”Journal of Appl. Phys., 2003, vol. 93(4) 2157-2163.
Franklin, N. R. et al., “Integration of suspended carbon nanotube arrays into electronic devices and electromechanical systems.”Appl. Phys. Lett., 2002, vol. 81(5) 913-915.
Fuhrer, M.S. et al., “High-Mobility Nanotube Transistor Memory.”Nano Letters, 2002, vol. 2(7) 755-759.
Homma, Y. et al., “Growth of Suspended Carbon Nanotubes Networks on 100-nm-scale Silicon Pillars.”Appl. Phys. Lett., 2002, vol. 81(12) 2261-2263.
Kinaret, J.M. et al., “A carbon-nanotube-based nanorelay”,Appl. Phys. Lett., 2003, vol. 82(8) 1287-1289.
Lee, K.H. et al., “Control of growth orientation for carbon nanotubes.”Appl. Phys. Lett., 2003, 82 (3) 448-450.
Radosavljevic, M. et al., “Nonvolatile molecular memory elements based on ambipolar nanotube field effect transistors.”Nano Letters, 2002, vol. 2(7) 761-764.
Robinson, L.A.W., “Self-Aligned Electrodes for Suspended Carbon Nanotube Structures.”Microelectronic Engineering, 2003, vol. 67-68, 615-622.
Rueckes, T., et al., “Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing”Science, 2000, vol. 289, 94-97.
Soh, H. T. et al., “Integrated nanotube circuits: Controlled growth and ohmic contacting of single-walled carbon nanotubes.”Appl. Phys. Lett., 1999, vol. 75(5) 627-629.
Sreekumar, T.V., et al., “Single-wall Carbon Nanotube Films”,Chem. Mater. 2003, vol. 15, 175-178.
Tans, S. et al., “Room-temperature transistor based on a single carbon nanotube.”Nature, 1998, vol. 393, 49-52.
Tour, J. M. et al., “NanoCell Electronic Memories.”J. Am. Chem Soc., 2003, vol. 125, 13279-13283.
Verissimo-Alves, M. et al., “Electromechanical effects in carbon nanotubes:Ab initioand analytical tight-binding calculations.”Phys. Rev. B, 2003, vol. 67, 161401-1-161401-4.
Wolf, S., Silicon Processing for the VLSI Era; vol. 2—Process Integration, Multi-Level-Interconnect Technology for VLSI and ULSI, 1990, Section 4.3 Materials for Multilevel Interconnect Technologies, pp. 189-191, Lattice Press, Sunset Beach.
Wolf, S., Silicon Processing for the VLSI Era; vol. 2—Process Integration, 1990, Section 4.7 Manufacturing Yield and Reliability Issues of VLSI Interconnects, pp. 260-273, Lattice Press, Sunset Beach.
Zhan, W. et al., “Microelectrochemical Logic Circuits.”J. Am. Chem. Soc., 2003, vol. 125, 9934-9935.

Affiliated with

Also associated with

Rating

NRAM bit selectable two-device nanotube array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with NRAM bit selectable two-device nanotube array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and NRAM bit selectable two-device nanotube array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3415727