Configuration enable bits for PLD configurable blocks

Details Configuration enable bits for PLD configurable blocks Configuration enable bits for PLD configurable blocks

2005-05-24

2005-05-24

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C365S230050, C365S189011

Reexamination Certificate

active

06897676

ABSTRACT:
A programmable logic device (PLD) includes columns of block memory interposed between columns of configurable logic blocks (CLBs). Each column of block memory includes a plurality of random access memories (RAMs) that share common configuration address lines that do not allow the RAMs in block memory column to be individually addressed. For some embodiments, each RAM in the column includes interface logic that selectively enables the RAM during configuration operations in response to a configuration enable bit, which may be provided to the PLD in a configuration bitstream and stored in a shadow register associated with the RAM.

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