Electrical computers and digital data processing systems: input/ – Input/output data processing – Concurrent input/output processing and data transfer
Reexamination Certificate
2003-09-04
2008-03-18
Huynh, Kim (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Concurrent input/output processing and data transfer
C710S006000, C710S019000, C710S020000, C710S005000
Reexamination Certificate
active
07346714
ABSTRACT:
It is an object of this invention to expand an SBP-3 protocol such that two data buffers can be independently controlled. To achieve this object, a target sends responses to status blocks corresponding to two commands included in one ORB in the SBP-3, and an initiator receives these responses to the commands independently of each other. The number of times of execution and time interval are designated for each command. The target repeats a command the designated number of times at the designated time interval.
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patent: 2002/0026550 (2002-02-01), Suzuki et al.
patent: 2003/0065865 (2003-04-01), Nakamura et al.
patent: 2003/0110329 (2003-06-01), Higaki et al.
patent: 2003/0182503 (2003-09-01), Leong et al.
patent: 2004/0057448 (2004-03-01), Nakamura
patent: 2004/0215840 (2004-10-01), Shimura
patent: 2000-250715 (2000-09-01), None
“IEEE Standard for a High Performance Serial Bus”, published from IEEE (The Institute of Electrical and Electronics Engineers, Inc.), Aug. 30, 1996.
P. Johansson, “Working Draft T10 Project 1467D Revision 11”, Feb. 5, 2002, Information Technology - Serial Bus Protocol 3 (SBP-3). (cited in JP OA dated Aug. 20, 2007, copy provided herewith).
Fukunaga Koji
Nakamura Atsushi
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Huynh Kim
Schneider Joshua D.
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