Nonvolatile semiconductor memory having a stress test circuit

Details Nonvolatile semiconductor memory having a stress test circuit Nonvolatile semiconductor memory having a stress test circuit

1989-04-20

1991-03-12

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Testing

365185, 36518906, 36518909, 365204, 36518911, G11C 2900, G11C 1604

Patent

active

049998137

ABSTRACT:
In a nonvolatile semiconductor memory, a plurality of nonvolatile semiconductor memory cells are arranged in a matrix form. Each of the memory cells is connected to a corresponding one of a plurality of bit lines and to a corresponding one of a plurality of word lines. The ends of the bit lines are commonly connected to a programming transistor for setting a programming mode through transistors for selecting the bit lines. The transistors are connected to column decoders and the word lines are connected to a row decoder. Furthermore, the other ends of the bit lines are connected to a common connecting line through transistors for setting a test mode and the common connecting line is connected to a node between the test mode transistors and a series circuit of a transistor and a dummy memory cell in a clamp circuit. The transistor of the clamp circuit is connected to a high voltage and the series circuit is connected to the ground. In the test mode, the programming transistor and the bit line selecting transistors are turned off and the test mode transistors and the transistor connected to the clamp circuit are turned on. Thus, a test voltage is applied to the memory cells through the common connecting line, the test mode transistors and the bit lines.

REFERENCES:
patent: 4612630 (1986-09-01), Rosier
patent: 4720818 (1988-01-01), Takeguchi
patent: 4779272 (1988-10-01), Kohda et al.
patent: 4819212 (1989-04-01), Nakai et al.
Atsumi et al., "Fast Programmable 256K Read Only Memory With On-Chip Test Circuits", IEEE Journal of Solid State Circuits, vol. SC-20, No. 1, Feb. 1985, pp. 422-427.

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