Nonvolatile semiconductor memory device with a multi-layer...

Details Nonvolatile semiconductor memory device with a multi-layer... Nonvolatile semiconductor memory device with a multi-layer...

2001-07-10

2003-04-29

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S320000, C257S321000, C257S637000, C257S640000, C257S324000

Reexamination Certificate

active

06555865

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
This invention related to the field of nonvolatile memory devices, and more particularly, to novel sidewall spacer structures for nonvolatile memory devices.
2. Description of the Related Art
Sidewall spacer structures are widely used in the manufacture of nonvolatile semiconductor memory devices for various reasons, for example, to isolate gate stacks from contact plugs.
One such sidewall spacer structure is disclosed in U.S. Pat. No. 6,001,687. This sidewall spacer structure is formed of silicon nitride and has many problems. For example, stresses occur at the interface between the surface of the silicon substrate and the silicon nitride spacer or between the sidewall of a floating gate formed of polysilicon and the silicon nitride spacer. Such stresses can degrade device characteristics such as charge retention. Also, many trap sites can exist in the silicon nitride spacer, degrading device characteristics such as endurance, reducing the reliability and durability of the nonvolatile memory devices.
Another sidewall spacer structure of the nonvolatile memory device is disclosed in U.S. Pat. No. 5,453,634. In this structure, as shown in
FIG. 1
, a silicon nitride layer
20
covers an etched-back oxide sidewall spacer
22
to protect a memory cell from invasion by mobile ions that deteriorate the charge-retention characteristics.
However, such a spacer structure also has several drawbacks. For example, as the integration density of semiconductor device increases, the space between the contact plug
24
and the sidewall spacer
22
becomes smaller and smaller. Consequently, misalignment easily occurs in etching the contact opening. Particularly, during the formation of the contact hole
26
, if misalignment occurs, the silicon nitride layer
20
on the sidewall spacers
22
can be perforated or damaged, as illustrated in FIG.
1
.
As a result, invasion of mobile ions from the contact hole
26
cannot be effectively prevented. This is a serious problem for the functionality and the reliability of nonvolatile memory devices. Particularly, once the nonvolatile memory device is programmed, it must remain programmed until it is subsequently erased. Therefore, during programming, the electrons trapped in the floating gate
8
should not become neutralized by ingress of charged ions from surrounding structures such as the contact hole
26
. However, with such damage to the silicon nitride layer
20
in the prior art, the electrons can get easily neutralized, degrading charge retention characteristics.
Also, substrate pitting can occur during the formation of the etched-back oxide sidewall spacer
22
, i.e., anisotropic etching of an oxide layer covering a stacked gate
10
. This often leads to a junction leakage problem and also a shallow junction structure cannot be properly achieved.
Additionally, because there is little etch selectivity between the etched-back oxide sidewall spacer
22
and an oxide field region
28
(
FIG. 2
) during the etching to form the oxide sidewall spacer
22
, over-etching of the field region
22
(a field loss or a recessed device isolation region) can occur, exhibiting undesirable device characteristics such as leakage current.
Furthermore, as shown in
FIG. 2
, with the prior art, especially when a borderless contact hole
30
that exposes both an active region
23
and the field region
28
through an interlevel dielectric layer
32
is formed, over-etching of the field region
28
can occur as indicated in the region designated as A, causing leakage current.
Accordingly, to overcome the above-mentioned problems and to improve the device characteristics such as charge-retention or endurance characteristics while reducing over-etching of the field region, there is an urgent need for improved sidewall spacer structures.
SUMMARY OF THE INVENTION
The present invention provides a nonvolatile memory device having high reliability with novel sidewall spacer structures. The gate stack structure for use in a nonvolatile memory device comprises a semiconductor substrate, a gate stack formed on the semiconductor substrate. The gate stack has a sidewall and a top surface. A muti-layer sidewall spacer structure is formed on the sidewall of the gate stack. The multi-layer sidewall spacer structure includes a first oxide layer, a first nitride layer, a second oxide layer, and a second nitride layer that are sequentially stacked. Thus, even if the second nitride layer is perforated or damaged during the formation of contact holes, sidewalls of the gate stack or nonvolatile memory cell can be protected with the first nitride layer from mobile ions invading from contact holes or surrounding structures. Also, etching damage to source/drain regions or field regions can be reduced. As a result, the device characteristics such as the charge retention and reliability of a memory cell can be significantly improved.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention that proceeds with reference to the accompanying drawings.


REFERENCES:
patent: 5234850 (1993-08-01), Liao et al.
patent: 5453634 (1995-09-01), Mori
patent: 5604367 (1997-02-01), Yang
patent: 5949706 (1999-09-01), Chang et al.
patent: 6001687 (1999-12-01), Chu et al.
patent: 6031264 (2000-02-01), Chien et al.
patent: 6144071 (2000-11-01), Gardner et al.

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