Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
Reexamination Certificate
2006-04-04
2006-04-04
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error count or rate
C714S718000, C714S736000
Reexamination Certificate
active
07024598
ABSTRACT:
A nonvolatile semiconductor memory device has a special test mode and circuitry for counting its own fail bits. During the test mode, test data is stored in the memory, and also in a special expected data buffer. The test data stored in the memory cells are then compared to that stored in the expected data buffer. Where there is no correspondence, fail bits are detected. The lack of correspondence is registered, counted, and output to a data output buffer block.
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Jeong Jae-Yong
Lee Sung-Soo
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Tu Christine T.
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