Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2005-09-27
2005-09-27
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Precharge
C365S063000
Reexamination Certificate
active
06950361
ABSTRACT:
A semiconductor memory device includes a sense amplifier, a pair of bit lines connected to the sense amplifier, first and second memory cell arrays connected to the bit lines, respectively, and including a plurality of memory cells each having a cell transistor and a ferroelectric capacitor, and first and second select transistors connected to the bit lines between the sense amplifier and the first and second memory cell arrays. The device further includes a first equalizing circuit connected to the bit lines closer to the first and second memory cell arrays than the first and second select transistors.
REFERENCES:
patent: 5828621 (1998-10-01), Tanzawa et al.
patent: 6188608 (2001-02-01), Maruyama et al.
patent: 10-255483 (1998-09-01), None
T. Sumi, et al., ISSCC Digest of Technical Papers, pp. 268-269, “FA 16.2: A 256KB Nonvolatile Ferroelectric Memory at 3V and 100NS”, Feb. 1994.
H. Koike, et al., IEEE Journal of Solid-State Circuits, vol. 31, No. 11, pp. 1625-1634, “A 60-NS 1-MB Nonvolatile Ferroelectric Memory with a Nondriven Cell Plate Line Write/Read Scheme”, Nov. 1996.
Kamoshida Masahiro
Takashima Daisaburo
Kabushiki Kaisha Toshiba
Le Vu A.
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