Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-30
2002-10-08
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C438S201000, C438S211000
Reexamination Certificate
active
06462373
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-342358, filed Dec. 1, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to nonvolatile semiconductor memory devices, and more particularly to a high density and high integration type nonvolatile semiconductor memory device having an improved memory cell structure.
Electrically data rewritable nonvolatile memory devices are widely used in high-speed ROMs and for mass storage devices. MOSFET type memory devices are generally used each of which has a stack gate structure comprising a charge accumulation layer or a floating gate and a control gate.
FIGS. 11A through 11C
are views showing an example of a memory cell having the stack gate structure.
FIG. 11A
is a plan view thereof,
FIG. 11B
is a sectional view taken along the line b—b of
FIG. 11A
, and
FIG. 11C
is a sectional view taken along the line c—c of FIG.
11
A.
In
FIGS. 11A through 11C
, for example, a trench for a device isolation is formed in a p-well layer
70
formed on an n-type silicon substrate. Inside of this trench, an insulation material for the device isolation, for example, a silicon dioxide is buried to form a plurality of device isolation regions
71
, thereby defining device forming regions
76
between the device isolation regions
71
.
On an overall surface of a channel region or the device forming region
76
which is device-isolated in such a manner, a thin tunnel insulation film
72
is formed which allows a tunnel current to flow. On the thin tunnel insulation film
72
, a charge accumulation layer
73
is formed. Then, on the charge accumulation layer
73
, a control gate
75
is further formed via an insulation film
74
which functions as an inter-gate insulation layer. The control gate
75
and the charge accumulation layer
73
are vertically processed in a self-aligning manner so that the side end portions are aligned as shown in
FIG. 11C
on a cross section in a direction of so-called word lines, namely, a direction in which the control gate
75
is extended. Furthermore, an n-type diffusion layer
77
is formed in a self-aligning manner in the device forming region
76
on both sides of each gate with respect to this side end portion. This n-type diffusion layer
77
is extended and formed between adjacent control gates
75
. In this manner, a nonvolatile memory cell is formed on each part of the gate portion.
On the other hand, on the cross section of
FIG. 11B
in the so-called bit line direction for supplying a potential to the diffusion layer
77
of the memory cell, the charge accumulation layer
73
is cut with the insulation film
74
on the device isolation region
71
so that the charge accumulation layer
73
is divided for each of the memory cells. Then the divided charge accumulation layer
73
is capacity-coupled with the control gate
75
via the insulation film
74
between gates
73
and
75
.
A data rewriting method in the nonvolatile memory cell having the above structure comprises the steps of applying a high voltage across the p-well layer
70
and the charge accumulation layer
73
to allow a tunnel current to flow through the tunnel insulation film
72
thereby exchanging the electric charge between the charge accumulation layer
73
and the p-well layer
70
, thereby modulating a quantity of the electric charge in the charge accumulation layer
73
in accordance with data being written.
A channel generation threshold voltage of a memory cell becomes higher with an increase in a negative electric charge in the charge accumulation layer
73
while the threshold voltage thereof becomes lower with an increase in a positive electric charge. Consequently, when electrons are tunnel-injected into the charge accumulation layer
73
, the threshold voltage is heightened with the result that the charge accumulation layer
73
is set to, for example, a datawritten state. When electrons are pulled out from the charge accumulation layer
73
, the threshold voltage becomes lower so that the charge accumulation layer
73
is set to, for example, an erased state.
FIG. 12
is a view showing one example of a nonvolatile semiconductor memory device using the memory cells. In
FIG. 12
, there is shown a case in which the memory cells are laid out in a NAND structure. A plurality of device forming regions
76
which are isolated in a plurality of device isolation regions
71
are extended and arranged in a direction of bit lines with the result that that a plurality of control gates
75
-
1
to
75
-n are extended and arranged in a direction which runs at right angle with the device forming region
76
. A plurality of memory cells are formed in a matrix-like configuration at each of the crossing points of the control gates
75
-
1
to
75
-n and the device forming region
71
, and n-type diffusion layers
77
are formed in the device forming region
76
between the respective control gates
75
-
1
to
75
-n.
As a consequence, a plurality of memory cells are connected in series in a direction of bit lines via the n-type diffusion layers
77
to constitute a unit block. Each of the unit blocks is connected to the bit line contact
81
via the selection gate
80
formed of a transistor. Outside of the selection gates
82
on the opposite side of the bit line contacts
81
in the unit blocks a common source line
83
is arranged and is connected via the n-type diffusion layer
77
. Incidentally, the bit line contacts
81
are connected to bit line signal lines not shown.
Along with an increase in the memory capacity of the nonvolatile semiconductor memory device, an increase in the density of the memory cell is extremely important, and a shrinkage in the memory size through the refinement of the memory cell is effective means for the realization of the increase in the density of the memory device. For this purpose, it is most important to suppress the disparity in the size of each of the memory devices in addition to the refinement of the stack gate and the device forming region or the like.
With respect to the stack gate structure, as explained in
FIG. 11C
, it is effective to align the side walls or side end portion in a self-aligning manner by processing collectively the second gate insulation film
74
and the charge accumulation layer
73
at the time of processing the control gate
75
.
On the other hand, with respect to the width of the device forming region or the width of the device isolation region, it is important to set the width of the charge accumulation layer
73
and the width of the device forming region to an equal size. There is proposed a self-aligning method for forming a charge accumulation layer in advance followed by forming in a self-aligning manner a device forming region in alignment with the charge accumulation layer (Japanese Patent Application No. 6-150241).
FIGS. 13A through 13C
are views showing one example of a memory cell having a self-aligning type device isolation structure.
FIG. 13A
is a plan view,
FIG. 13B
is a sectional view taken along the line b—b of
FIG. 13A
, and
FIG. 13C
is a sectional view taken along the line c—c of
FIG. 13A
in the same manner.
For example, as shown in
FIG. 13B
, a trench for the device isolation is formed inside of the p-well layer
90
. Inside of the trench, an insulation material for the device isolation, for example, silicon dioxide is buried, so that a device isolation region
91
is formed. On the overall surface of the channel region on the p-well layer
90
which is device-isolated, a thin tunnel insulation film
92
is formed which allows a tunnel current to flow.
On the tunnel insulation film
92
, as shown in
FIGS. 13A and 13C
, a conductive layer
93
a
which forms a part of the charge accumulation layer
93
and which has a side end portion aligned with the device forming region
96
is formed. On the conductive layer
93
a
, another conductive layer
93
b
is formed,
Aritome Seiichi
Iguchi Tadashi
Iizuka Hirohisa
Koido Naoki
Narita Kazuhito
Flynn Nathan J.
Kabushiki Kaisha Toshiba
Quinto Kevin
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