Nonvolatile semiconductor memory device covered with...

Details Nonvolatile semiconductor memory device covered with... Nonvolatile semiconductor memory device covered with...

2000-04-25

2004-12-07

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C257S316000, C257S317000, C257S325000, C257S326000, C257S341000, C257S368000, C257S390000, C257S909000, C257S640000, C257S649000

Reexamination Certificate

active

06828624

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-118115, filed Apr. 26, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.
As is well known in the art, a semiconductor memory has cell transistors and peripheral transistors formed on the same substrate. As one example thereof, an electrically erasable and programmable read only memory in which data erasing and programming can be electrically effected is well known.
FIG. 1
shows an EEPROM. That is,
FIG. 1
schematically shows the construction of cell transistors (including selection gate transistors) and peripheral transistors of a conventional NAND type EEPROM.
The construction of the cell transistor and peripheral transistor of the NAND type EEPROM is explained below according to the manufacturing process thereof.
FIGS. 2A
to
2
D show the manufacturing process of the cell transistors and peripheral transistors of the conventional NAND type EEPROM.
First, as shown in
FIG. 2A
, for example, after a well region and element isolation region (neither of them is shown in the drawing) are formed in the surface area of a silicon substrate
101
, a thermal oxidation film
102
used as a gate insulating film or tunnel oxide film is formed on the well region.
Then, in the memory cell region, gate electrodes
103
of stacked gate structure are formed on the thermal oxidation film (tunnel oxide film)
102
and, in the peripheral circuit region, gate electrodes
104
of single-layered structure are formed on the thermal oxide film (gate insulating film)
102
.
The gate electrode
103
in the memory cell region has a well known structure in which, for example, a control gate electrode
103
c
is stacked on a floating gate
103
a
used as a charge storing layer while an ONO film (oxide film
itride film/oxide film)
103
b
used as an inter-gate insulating film is disposed therebetween.
Next, as shown in
FIG. 2B
, post-oxidation films
105
for restoring the gate electrodes
103
,
104
from the processing damage are formed.
Then, as shown in
FIG. 2C
, impurity
106
is implanted to form source and drain diffusion regions of the respective transistors.
After this, as shown in
FIG. 2D
, the implanted impurity
106
is activated by annealing and driven towards the channel region side to form source and drain diffusion layers
106
′.
Next, after an inter-level insulating film
107
is formed on the structure, contacts
108
and inter-connection layers
109
connected to the electrodes
104
and contacts
110
and bit lines
111
connected to the source/drain diffusion layers
106
′ are formed to form the cell transistors and peripheral transistors of the structure shown in FIG.
1
.
However, if the conventional cell transistors and peripheral transistors are formed as described above, the length of the overlap area of the source/drain diffusion layer
106
′ over the gate electrode
103
or
104
varies depending on the condition of the annealing process effected after the impurity
106
is implanted.
For example, if the annealing process is not sufficiently effected and the source/drain diffusion layer
106
′ does not overlap and is offset from the gate electrode
103
or
104
, the offset portion acts as a parasitic resistor to prevent a sufficiently large drain current from flowing in the device.
On the other hand, if the annealing process is excessively effected and the source/drain diffusion layer
106
′ extends deeply into the channel region, the short channel effect becomes significant and the source-drain withstand voltage is lowered, thereby degrading the device characteristic.
Generally, the gate length in the memory cell is shorter than that in the peripheral transistor. Therefore, the short channel effect in the memory cell tends to become more noticeable. That is, if the annealing process is sufficiently effected for the peripheral transistor, there occurs a possibility that punch through may occur in the cell transistor and selection transistor.
In the case of NAND type EEPROM, since the source and drain diffusion layers
106
′ of the memory cells are satisfactory if they can electrically connect the cells which are serially arranged, it is not necessary to overlap the source/drain diffusion layer
106
′ over the gate electrode
103
. That is, it can be the that the annealing process after the impurity
106
is implanted is effected to the least possible degree from the viewpoint of the characteristic of the cell transistor and selection transistor.
Further, in the case of the post-oxidation amount after the gate processing, the post-oxidation for sufficiently compensating for the processing damage is necessary, but the post-oxidation increases the bird's beak amount. In a case where the memory cell has a short gate, an increase in the bird' beak amount by the post-oxidation (refer to a portion A in
FIG. 1
, for example) lowers the coupling ratio, degrades the programming and erasing characteristics and is not preferable.
In the case of the peripheral transistor, since the gate is relatively long, it is permitted to sufficiently effect the post-oxidation (refer to a portion B in
FIG. 1
, for example).
Thus, since the NAND type EEPROM includes transistors having different gate lengths and the post-oxidation amount and the most suitable annealing condition for impurity diffusion are different depending on the gate lengths of the transistors, the difference causes a main factor which lowers the process margin.
BRIEF SUMMARY OF THE INVENTION
A nonvolatile semiconductor memory device comprises: a semiconductor substrate having a peripheral circuit region and a memory cell region; a first element region provided in the memory cell region; a second element region provided in the peripheral circuit region; a memory cell having source and drain diffusion layers each provided in the first element region; a peripheral transistor having source and drain diffusion layers each provided in the second element region; an element isolation region being in contact with the first element region; an insulating film covering the memory cell, the peripheral transistor and the element isolation region and containing an insulator different from the element isolation region, the insulating film being harder for an oxidizing agent to pass therethrough, compared with a silicon oxide film, and a surface of the insulating film being oxidized; an inter-level insulating film provided on the surface of the insulating film, the inter-level insulating film containing an insulator different from the insulating film; a contact hole provided in the inter-level insulating film and the insulating film, the contact hole reaching at least one of the source and drain diffusion layers of the memory cell and overlapping the element isolation region; and a contact plug provided in the contact hole, the contact plug being in contact with at least one of the source and drain diffusion layers of the memory cell, the insulating film and the inter-level insulating film.


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