Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-07-26
2011-07-26
Thai, Luan C (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000, C438S593000, C438S591000
Reexamination Certificate
active
07985650
ABSTRACT:
A nonvolatile semiconductor memory device includes a floating gate electrode which is selectively formed on a main surface of a first conductivity type with a first gate insulating film interposed therebetween, a control gate electrode formed on the floating gate electrode with a second gate insulating film interposed therebetween, and source/drain regions of a second conductivity type which are formed in the main surface of the substrate in correspondence with the respective gate electrodes. The first gate electrode has a three-layer structure in which a silicon nitride film is held between silicon oxide films, and the silicon nitride film includes triple coordinate nitrogen bonds.
REFERENCES:
patent: 5739569 (1998-04-01), Chen
patent: 6191445 (2001-02-01), Fujiwara
patent: 6674138 (2004-01-01), Halliyal et al.
patent: 6794712 (2004-09-01), Fujiwara
patent: 6858906 (2005-02-01), Lee et al.
patent: 7098147 (2006-08-01), Nansei et al.
patent: 7229880 (2007-06-01), Dong et al.
patent: 2002/0118566 (2002-08-01), Jong et al.
patent: 2002/0142624 (2002-10-01), Levy et al.
patent: 2003/0100153 (2003-05-01), Kunori
patent: 2004/0061169 (2004-04-01), Leam et al.
patent: 2004/0185647 (2004-09-01), Dong et al.
patent: 2005/0212074 (2005-09-01), Sera et al.
patent: 01-169932 (1989-07-01), None
patent: 01-307272 (1989-12-01), None
patent: 05-036991 (1993-02-01), None
patent: 08-031958 (1996-02-01), None
patent: 09-064205 (1997-03-01), None
patent: 09-153492 (1997-06-01), None
patent: 2000-004018 (2000-01-01), None
patent: 2003-347543 (2003-12-01), None
patent: 2004-095918 (2004-03-01), None
patent: WO 2004/023549 (2004-03-01), None
Matsushita et al., “Semiconductor Device Manufacturing Method,” U.S. Appl. No. 10/941,814, filed Sep. 16, 2004.
Notification of Reasons for Rejection mailed Jan. 6, 2009, from the Japanese Patent Office in corresponding Japanese Patent Application No. 2004-185497, and English language translation thereof.
Notification of the First Office Action, The Patent Office of the People's Republic of China, in Chinese Application No. 200510079464.7, dated Oct. 12, 2007.
S. Tsujikawa et al., “An Ultra-Thin Silicon Nitride Gate Dielectric With Oxygen-Enriched Interface (OI-SiN) for CMOS With EOT of 0-9 nm and Beyond,” Symposium on VLSI Technology, Digest of Technical Papers, pp. 202-203 (2002).
Wang, Xue-Seng et al., Crystalline Si3N4 thin films on Si(111) and the 4×4 reconstruction on Si3N4(0001), Rapid Communications, The American Physical Society, Physical Review B, vol. 60, No. 4, pp. R2146-R2149.
Xiang et al., “Extending the Life of N/O Stack Gate Dielectric With Gate Electrode Engineering,” IWGI, pp. 134-139 (2003).
Yang et al., “Reliability considerations in scaled SONOS nonvolatile memory devices,” Solid-State Electronics, 1999, pp. 2025-2032, vol. 43.
Notification of the First Office Action mailed Jul. 10, 2009, from The Patent Office of the People's Republic of China in corresponding Chinese Application No. 200810074158.8, and English language translation thereof.
Matsushita Daisuke
Mitani Yuichiro
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Thai Luan C
LandOfFree
Nonvolatile semiconductor memory device and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile semiconductor memory device and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory device and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2640565