Nonvolatile semiconductor memory device and method for...

Details Nonvolatile semiconductor memory device and method for... Nonvolatile semiconductor memory device and method for...

2000-12-04

2002-03-19

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S270000, C438S276000, C438S286000

Reexamination Certificate

active

06358799

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and a method for fabricating the same, and also relates to a semiconductor integrated circuit device.
In memories for portable units and memory-incorporated logic VLSI's, the technologies for nonvolatile memories have become increasingly important because it is demanded to reduce the costs per bit and to enhance electrical rewrite functions. For such purposes, various structures and fabrication processes have been suggested.
Hereinafter, conventional nonvolatile memories will be described while giving the outlines of such structures and processes.
FIG. 23
shows the cross section of a nonvolatile semiconductor memory device having a so-called “split-gate type” structure. Such a device was suggested by G. Samchisa et al. in IEEE J. Solid-State Circuits, pp. 676, 1987.
In the device shown in
FIG. 23
, a tunnel oxide film
102
, a floating gate
103
and a capacitive insulating film
104
are formed on the upper surface of a semiconductor substrate
101
. A control gate
105
is further formed so as to cover the floating gate
103
. Also, in the semiconductor substrate
101
, a source region
106
, which have been doped with an impurity at a high concentration, is formed in a region partially overlapping with the control gate
105
, and a drain region
107
, which have been doped with an impurity at a high concentration, is formed in a region partially overlapping with the floating gate
103
.
The device shown in
FIG. 23
has a so-called “split-gate structure” in which the control gate
105
and the floating gate
103
are disposed via the capacitive insulating film over a channel region between the source region
106
and the drain region
107
. The floating gate
103
functions as a node in which information is stored and the charged states thereof are made to correspond to “0” and “1” of the information. By utilizing the fact that the threshold voltage as viewed from the control gate
105
is varied in accordance with the amount of charge accumulated in the floating gate
103
, the reading of data is performed.
The writing of data utilizes a strong lateral high electric field, which is generated in a boundary between a “drain potential expansion region” in a region immediately under the floating gate
103
and an “inversion channel region” in a region immediately under the control gate
105
. By utilizing the phenomenon that channel hot electrons, which have obtained high energy as a result of the acceleration caused by the lateral high electric field, are injected into the oxide film so as to reach the floating gate
103
, a relatively high electron injection efficiency is achieved. Such an electron injection is called a “source-side injection”.
The erasure of data is performed by taking out the electrons in the floating gate
103
into the drain region
107
by the use of a Fowler-Nordheim (FN) tunneling phenomenon. In order to utilize the FN tunneling phenomenon, a high electric field of about 10.5 MV/cm to about 11 MV/cm is required to be formed in the oxide film
102
. Since the tunnel oxide film
102
of the device of the above-cited document is as thick as 20 nm, a high voltage of about 21 V is applied to the drain region
107
when data is erased.
Since the structure shown in
FIG. 23
uses the drain region
107
in both cases of writing and erasing data, the compatibility between the operating speed and the reliability is insufficient.
In order to make the operating speed and the reliability compatible, a device shown in
FIG. 24
has been proposed. This device was disclosed by S. Kianian et al. in IEEE Symposium VLSI Technology 1994, Digest of Technical Papers, pp. 71.
In the device shown in
FIG. 24
, a gate oxide film
204
, a floating gate
203
and a control gate
205
partially overlapping with the floating gate
203
are formed over a semiconductor substrate
201
. In the semiconductor substrate
201
, an extremely thick source region
206
, which have been doped with an impurity at a high concentration, is formed in a region partially overlapping with the floating gate
203
, and a drain region
207
, which have been doped with an impurity at a high concentration, is formed in a region partially overlapping with the control gate
205
. And the control gate
205
and the floating gate
203
are disposed via a tunnel oxide film
202
over a channel region between the source region
206
and the drain region
207
.
The writing of data utilizes a strong lateral high electric field which is generated in a boundary between an “expansion region” of a high potential in the channel region (the “expansion region” has been generated by applying a voltage as high as 11 V to the source region
206
) and an “inversion channel region” in a region immediately under the control gate
205
. A phenomenon that channel hot electrons, which have obtained high energy by the lateral high electric field, are injected into the oxide film so as to reach the floating gate
203
is utilized. This data write operation is performed by exchanging the voltages to be applied to the source region
206
and the drain region
207
with each other. However, in the other respects, this operation is performed in the same way as the data write operation performed by the device shown in FIG.
23
. In the device shown in
FIG. 24
, the injection efficiency is further increased by the thick source region
206
which is capacitively coupled to the floating gate
203
.
The erasure of data is performed by taking out the electrons in the floating gate
203
into the control gate
205
by applying a voltage of about 14 V to the control gate
205
and by utilizing the FN tunneling phenomenon, thereby trying to improve the erasure characteristics. In the device shown in
FIG. 24
, the effective channel length is decreased by the thick source region
206
which is employed for increasing the capacitance coupling with the floating gate
203
. Thus, this device is not appropriate for further reducing the size of a memory cell.
FIG. 25
shows the cross section of a nonvolatile semiconductor memory device which is designed to shorten a write time or to reduce a write voltage by increasing a write efficiency. This device is disclosed by Nakao, et al. in Japanese Laid-Open Publication No. 7-115142.
The device shown in
FIG. 25
uses a semiconductor substrate
301
with a step
302
formed on the surface thereof. The surface of the semiconductor substrate
301
is divided by this step
302
into a surface at a relatively high level (first surface region) and a surface at a relatively low level (second surface region). A tunnel oxide film
303
, a floating gate
304
, a capacitive insulating film
305
and a control gate
306
are stacked in this order over the step
302
. In the surface of the semiconductor substrate
301
, a high-concentration source region
307
and a high-concentration drain region
308
, both of which have been doped with an impurity at a high concentration, are formed. A thin high-concentration impurity layer (having a thickness of 0.1 &mgr;m or less)
309
extends from the high-concentration drain region
308
along the sides of the step
302
to reach the first surface region. Since the thin high-concentration impurity layer
309
functions as a drain region, the region between the high-concentration source region
307
and the high-concentration impurity layer
309
becomes a channel region. The floating gate
304
is formed so as to overlap the channel region and to cover the high-concentration impurity layer
309
.
In such a structure, since the floating gate
304
is located in the directions of the velocity vectors of channel hot electrons, the channel hot electron injection efficiency is presumably increased.
Next, a method for fabricating the nonvolatile semiconductor memory device shown in
FIG. 25
will be described with reference to
FIGS. 26A
to
26
E.
First, as shown in
FIG. 26A
, an oxide film
311
is formed as a mask for forming a step in the semiconductor substrate
3

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