Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-09-11
2010-12-21
Garber, Chares D (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S294000, C438S295000, C438S296000, C438S359000, C438S404000, C438S412000, C257S392000, C257S501000, C257S506000, C257S374000, C257S540000, C257SE21540, C257SE21644, C257SE21206, C257SE21628, C257SE21630, C257SE27060, C257SE29020
Reexamination Certificate
active
07855116
ABSTRACT:
In a nonvolatile semiconductor memory device which has a nonvolatile memory cell portion, a low-voltage operating circuit portion of a peripheral circuit region and a high-voltage operating circuit portion of the peripheral circuit region formed on a substrate and in which elements of the above portions are isolated from one another by filling insulating films, the upper surface of the filling insulating films in the high-voltage operating circuit portion lies above the surface of the substrate and the upper surface of at least part of the filling insulating films in the low-voltage operating circuit portion is pulled back to a portion lower than the surface of the substrate.
REFERENCES:
patent: 5174933 (1992-12-01), Toh et al.
patent: 6706646 (2004-03-01), Lee et al.
patent: 7105397 (2006-09-01), Hieda et al.
patent: 7338860 (2008-03-01), Kwon
patent: 7416987 (2008-08-01), Hieda et al.
patent: 2004/0058499 (2004-03-01), Ishitsuka et al.
patent: 2005/0093047 (2005-05-01), Goda et al.
patent: 2005/0106822 (2005-05-01), Lee et al.
patent: 2006/0134845 (2006-06-01), Pham et al.
patent: 2006/0270170 (2006-11-01), Arisumi et al.
patent: 2008/0182381 (2008-07-01), Kiyotoshi
patent: 3178412 (2001-04-01), None
patent: 2001-319927 (2001-11-01), None
patent: 2004-039902 (2004-02-01), None
patent: 2004-228557 (2004-08-01), None
patent: 2005-353892 (2005-12-01), None
patent: 2006-332442 (2006-12-01), None
Heo et al. “Void free and low stress shallow trench isolation technology using P-SOG for sub 0.1 um device”, Symposium on VLSI technology, pp. 132-133, 2002.
Notice of Rejection dated Nov. 15, 2009, issued by the Japanese Patent Office in a counterpart application No. 2007-239767 (3 pages).
Abdelaziez Yasser A
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Garber Chares D
Kabushiki Kaisha Toshiba
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