Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-10
2001-11-13
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06316314
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of fabricating such a device, and particularly to a nonvolatile semiconductor memory device in which a dummy pattern is formed in a boundary area between a memory cell area and a peripheral circuit area, and a method of fabricating such a device.
2. Description of the Related Art
A nonvolatile memory having a floating gate comprises a memory cell area, a peripheral circuit area containing transistors, and a boundary area that forms the boundary between the memory cell area and the peripheral circuit area.
In the prior art, such a nonvolatile memory was fabricated by processes such as shown in
FIGS. 1-8
. The fabrication method of the prior art is disclosed in Japanese Patent Laid-open No. 151580/94.
In this fabrication method, as shown in
FIG. 1
, element isolating area
14
and gate insulating film
12
are first formed on, for example, p-type silicon substrate
10
. Polysilicon
16
is next formed over the entire surface, and polysilicon
16
of the memory cell area is then patterned using resist pattern
18
to form floating gate electrodes
20
. At this time, the polysilicon of the peripheral circuit area is not removed and remains so as to prevent implantation of ions into the peripheral circuit area when ions for channel stopping are implanted in the next process.
Next, as shown in
FIG. 2
, ions are implanted for a channel stopper. In this case, silicon substrate
10
is p-type, and boron (B) ions, which can form a p-type area, are therefore implanted. The purpose of this ion implantation is as follows:
The width of element isolating areas
14
that are to be formed between floating gate electrodes shrinks with the miniaturization of memory cells. A decrease in the width of element isolating area
14
means that the element isolating areas are also thinner than in a case in which element isolating areas are sufficiently large, and this leads to a drop in element isolating capability and the occurrence of adverse effects such as the flow of current between adjacent channels. To prevent such adverse effects, a channel stopper, which is a p-type area of higher concentration than silicon substrate
10
, is formed inside and on the lower surface of element isolating areas.
After removing resist pattern
18
, resist pattern
22
is provided on the memory cell area and polysilicon
16
of the peripheral circuit area is removed by dry etching, as shown in FIG.
3
. At this time, gate insulating film
12
below polysilicon
16
is also partially removed.
Next, resist pattern
22
is removed, and after removing gate insulating film
12
of the peripheral circuit area by wet etching, an ONO film (a three-layer structure of silicon oxide film-silicon nitride film-silicon oxide film) is formed over the entire surface as shown in FIG.
4
. This ONO film
24
is an insulating film for preventing the loss of the charge held by floating gate electrodes
20
. Although this ONO film
24
has ideal functions if formed as a film above floating gate electrodes
20
, it is not appropriate as a gate insulating film of transistors of the peripheral circuit area, and ONO film
24
of the peripheral circuit area is therefore eliminated using resist pattern
25
as shown in FIG.
5
. Methods of removing the ONO film include dry etching and wet etching.
Next, as shown in
FIG. 6
, gate oxidation is carried out and gate insulating film
26
is formed in the peripheral circuit area.
Polysilicon
30
is next formed over the entire surface as shown in
FIG. 7
, and control gate electrodes
30
are patterned in the memory cell area using resist pattern
28
. The removal of polysilicon
30
by patterning also encroaches into element isolating area
14
below polysilicon
30
in area
38
.
Finally, resist pattern
28
is eliminated, and, as shown in
FIG. 8
, the polysilicon of the peripheral circuit area is patterned using resist pattern
32
to form gate electrodes
34
. At this time, resist pattern
32
is formed to cover area
38
so that the film thickness of element isolating area
14
below area
38
is not etched and diminished as an element isolation film. As a result, dummy pattern
36
composed of polysilicon is left in the boundary area between the memory cell area and the peripheral circuit area. This dummy pattern
36
surrounds the memory cell area and connects to ground when the memory cell is used.
The dry etching or wet etching that is used when removing the ONO film from the peripheral circuit area in the prior-art fabrication method described hereinabove has the following problems:
When dry etching is used, there is the disadvantage that over-etching may encroach into the silicon substrate in the formation area of the gate insulating film. This problem occurs because the etching rate of nitride film and the etching rate of oxide film in the ONO film are substantially equal, and it is therefore difficult to carry out etching such that only the oxide film of the gate insulating film formation area remains. Etching into the silicon substrate in the formation area of the gate insulating film causes problems such as deterioration of the withstand voltage of the gates, leakage of current at the field end, and a decrease in the ON current of transistors.
In the case of wet etching, the use of nitride film etching liquid can introduce a difference between the etching rate of the nitride film and the etching rate of the oxide film, but an oxide film must be formed as a mask instead of a resist because a resist cannot serve as a mask against the wet etching liquid of the nitride film. When this oxide film for masking is removed, however, there is the problem that the uppermost oxide film layer of the ONO film in the memory cell area is also removed.
Removal of the uppermost oxide layer of the ONO film in the memory cell area causes such problems as variation in the nonvolatile memory operating properties and a reduction in the product yield.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a construction of a nonvolatile semiconductor memory device that does not cause the above-described problems during fabrication and a method of fabricating a nonvolatile semiconductor memory device of this construction.
The nonvolatile semiconductor memory device of this invention is provided with: a memory cell area including nonvolatile memory, a peripheral circuit area including circuits for controlling this nonvolatile memory, and dummy pattern provided in the boundary area between the memory cell area and the peripheral circuit area.
In the first embodiment, this dummy pattern is made up of: a conductive material that constitutes the control gate electrodes of the nonvolatile memory, and residue of an insulative material that constitutes an insulating film between the floating gate electrodes and control gate electrodes that remain without being removed in the fabrication process; this residue being covered by the conductive material.
In the second embodiment, the dummy pattern is made up of: a first conductive material that constitutes the floating gate electrodes of the nonvolatile memory, a second conductive material that constitutes the control gate electrodes of the nonvolatile memory, and an insulative material that makes up the insulating film between the floating gate electrodes and the control gate electrodes.
The method of fabricating the nonvolatile semiconductor memory device of this invention is a method of fabricating a nonvolatile semiconductor memory device provided with: a memory cell area including nonvolatile memory, a peripheral circuit area including circuits for controlling this nonvolatile memory, and a dummy pattern provided in the boundary area between the memory cell area and the peripheral circuit area.
The first embodiment of the fabrication method includes a step of providing, in a boundary area between the memory cell area and peripheral circuit area, a dummy pattern that is made up of: residue that is the
Booth Richard
NEC Corporation
Young & Thompson
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