Nonvolatile semiconductor memory device and an optimizing progra

Details Nonvolatile semiconductor memory device and an optimizing progra Nonvolatile semiconductor memory device and an optimizing progra

1992-04-30

1994-03-29

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

36518901, 36518911, 365185, G11C 700

Patent

active

052991628

ABSTRACT:
A nonvolatile semiconductor memory device particularly relates to an EEPROM having NAND-structured cells, and an optimizing programming method thereof. The device includes a memory cell array arranged as matrix having NAND cells formed by a plurality of serially-connected memory cells each of which is formed by stacking a charge storage layer and a control gate on a semiconductor substrate, and enables electrical erasing by the mutual exchange of a charge between the charge storage layer and the substrate, a data latch circuit, a high voltage supply circuit, a current source circuit, a program checking circuit, and a program status detecting circuit. The programming state is optimized while being unaffected by the variance of process parameters, over-programming is prevented by the use of a verifying potential, and the performance of the chip is enhanced by automatically optimizing the programming with a chip's internal verification function. External control is not required, which enhances performance of the overall system. Also, a page buffer of an existing flash memory having the page mode function is employed, which is applicable to the currently used products.

REFERENCES:
patent: 4887242 (1989-12-01), Hashimoto
patent: 4996669 (1991-02-01), Endoh et al.
patent: 5075890 (1991-12-01), Itoh et al.
patent: 5105384 (1992-04-01), Noguchi et al.

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