Nonvolatile semiconductor memory device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S593000, C257SE21179, C257SE21422, C257SE21680

Reexamination Certificate

active

11430170

ABSTRACT:
A nonvolatile semiconductor memory device including a memory cell and a selection transistor, and the memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate formed on the substrate via a second gate insulation film, and a pair of second diffusion layers formed in the substrate positioned on the opposite sides of the selection gate and one of which is electrically connected to one of the pair of first diffusion layers.

REFERENCES:
patent: 6894341 (2005-05-01), Sugimae et al.
patent: 2006/0060911 (2006-03-01), Sakuma et al.
patent: 2007/0128802 (2007-06-01), Aritome
patent: 4-253375 (1992-09-01), None
patent: 11-145429 (1999-05-01), None
patent: 2002-50703 (2002-02-01), None
patent: 2002-217318 (2002-08-01), None
patent: 2002-280463 (2002-09-01), None
Y. Sasago, et al., IEEE IEDM, pp. 952-954, “10-MB/s Multi-Level Programming of GB-Scale Flash Memory Enabled by New AG-and Cell Technology,” 2002.

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