Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

1987-03-25

1989-11-07

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Testing

365185, 36518905, 365195, G11C 1140, G11C 2900

Patent

active

048796891

ABSTRACT:
A nonvolatile semiconductor memory device comprising a matrix array of memory cells, word lines for driving the rows of memory cells, bit lines for reading data from columns of memory cells, a plurality of first MOS transistors provided for these bit lines, respectively, a second MOS transistor having a source coupled to the bit lines by the first MOS transistors, a drain coupled to a VCC terminal, and a gate connected to receive a predetermined bias voltage, a row decoder for selecting one of the word lines in accordance with a row-address signal, and a column decoder for turning on one of the first MOS transistors in accordance with a column-address signal. The memory device further has a CE terminal for receiving a test-mode signal, an OE terminal for receiving first and second control signals, and a control circuit for detecting a test mode, thereby prohibiting the operation of the row decoder in response to the first control signal, and permitting the operation of the row decoder in response to the second control signal.

REFERENCES:
patent: 4404659 (1983-09-01), Kihara et al.
patent: 4451903 (1984-05-01), Jordan
patent: 4758984 (1988-07-01), Yoshida

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