Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2000-07-28

2002-01-22

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S272000

Reexamination Certificate

active

06340611

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates a nonvolatile semiconductor memory device, and more particularly to a stacked gate structure of a memory cell transistor.
EEPROM is a type of nonvolatile semiconductor memory device capable of rewriting data electrically. Each memory cell in EEPROM is generally composed of an FETMOS transistor which has a floating gate between a control gate and a channel region and whose threshold voltage can be varied. EEPROMs are available in several types, depending on the way of connecting memory cell transistors. They include the NOR type, NAND type, AND type, and DINOR type.
FIG. 1A
is a plan view of a memory cell array of a conventional NAND EEPROM memory cell array.
FIG. 1B
is a sectional view taken along a line
1
B—
1
B of FIG.
1
A.
As shown in
FIGS. 1A and 1B
, element isolating regions
102
are formed in a p-type silicon substrate
101
. The element isolating regions
102
mark off one semiconductor active region
103
(element region) from another. The active regions
103
in the memory cell array have a parallel line pattern. The element isolating regions
102
are made of silicon dioxide. Although a high-concentration p
+
-type region called a channel stopper is usually formed below each element isolating region
102
in the substrate
101
to prevent the conductivity type directly under the element isolating region from being inverted, the channel stopper will be omitted in the present specification.
On the active regions
103
, first gate insulating films
104
are formed thin enough to allow tunnel current to flow. The gate insulating films
104
are made of silicon dioxide (in the present specification, for the sake of convenience, the first gate insulating films
104
are referred to as tunnel oxide films).
On the tunnel oxide films
104
, floating gates
105
are formed. The floating gates
105
are made of conductive polysilicon and function as charge storage layers that store charges. Each memory cell transistor is provided with one floating gate
105
, which is isolated from the others. The threshold voltage of each memory cell transistor is adjusted according to the amount of electrons stored in the corresponding floating gate
105
. Data is converted into the level of the threshold voltage and stored.
On the floating gates
105
, a second gate insulating film
106
is formed. The second gate insulating film
106
is generally made of a stacked layer film called an ONO film (in the present specification, for convenience's sake, the second gate insulating film
106
is referred to as the ONO film). In the stacked layer film, silicon dioxide, silicon nitride, and silicon dioxide are stacked in that order.
On the ONO film
106
, control gates
107
are formed. The control gates
107
are made of conductive polysilicon and formed into continuous lines in the direction of the row in the memory cell array and function as word lines (in the specification, for convenience's sake, the control gates
107
are referred to as the word lines).
The floating gates
105
and word lines
107
are formed by achieving consecutive etching using the same mask. As a result, the edges of the floating gates
105
align with those of the word lines
107
in the direction of the channel width (i.e., in the direction of the row in the figure). Hereinafter, the gate structure where the floating gate
105
and word line
107
are stacked is referred to as a stacked gate
108
. With the stacked gates
108
and element isolating regions
102
as a mask, n-type source/drain regions
109
are formed by ion-implanting n-type impurities into the active regions
103
.
In the memory cell array, the element isolating regions
102
are formed by local thermal oxidation of the silicon substrate
101
. A typical example of this formation method is the LOCOS method.
FIGS. 2A and 2B
are sectional views to help explain the procedure of the LOCOS method.
As shown in
FIG. 2A
, a buffer oxide film (silicon dioxide)
110
is formed on a silicon substrate
101
. Then, the buffer oxide film excluding the regions in which the element isolating regions
102
are to be formed is covered with a silicon nitride film
111
. In this state, using the nitride film
111
as a barrier to oxidation, the surface of the silicon substrate
101
is subjected heavily to thermal oxidation as shown in FIG.
2
B. As a result, the element isolation regions
102
are formed.
In the LOCOS method, however, during oxidation, a wedge-shaped oxide film
112
called a bird's beak develops along the interface between the silicon substrate
101
and the nitride film
111
. This results in the conversion difference “&Dgr;” between the dimension “Wactual” of the actually formed element isolating region
102
and the dimension “Wdesign” of the element isolating region
102
in design.
As described above, because in the LOCOS method, the actual dimension “Wactual” is larger than the design dimension “Wdesign,” it is very difficult to form such microscopic element isolating regions
102
that, for example, the actual dimension “Wactual” is equal to or less than 0.5 &mgr;m.
Moreover, in the LOCOS method, it is difficult to form the element isolating regions
102
deep or thick in the silicon substrate
101
. As the dimension “W” will be made smaller in the future, it will be much more difficult to form the element isolating regions
102
deep. The element isolating regions
102
formed in the memory cell array are exposed to an etching environment, especially when the stacked gates are processed. As a result, the thicknesses of the regions excluding the portions covered with the stacked gates decrease during the processing. The element isolating regions whose film thickness has been reduced have poorer insulation capabilities.
One of element isolating techniques to solve the above problem is a trench element isolating method of forming trenches in a silicon substrate and filling the trenches with insulating material.
FIG. 3A
is a plan view of a conventional NAND EEPROM memory cell array using the trench element isolating method.
FIG. 3B
is a sectional view taken along a line
3
B—
3
B of FIG.
3
A. In these figures, the same parts as those in
FIGS. 1A and 1B
are indicated by the same reference symbols.
As shown in
FIGS. 3A and 3B
, trenches
121
are made in the substrate
101
. The trenches
121
are filled with an insulating materiel
122
. The insulating material
122
is made of silicon dioxide and functions as an element isolating region. Hereinafter, the insulating material is referred to as the trench element isolating region
122
.
FIGS. 4A and 4B
are sectional views to help explain the procedure of the trench element isolating method. As shown in
FIG. 4A
, the regions excluding the regions in which trench element isolating regions
122
are to form on the silicon substrate
101
are covered with a silicon nitride
123
. In this state, with the nitride film
123
as a barrier to etching, the silicon substrate
101
is subjected to etching to form trenches
121
.
Then, after silicon dioxide has been deposited on the entire surface of the silicon substrate
101
, the deposited silicon dioxide is etched back by RIE techniques or CMP techniques and the trenches
121
are filled with silicon dioxide as shown in FIG.
4
B. As a result, the trench element isolating regions
122
have been formed.
With such a trench element isolating method, the aforementioned conversion difference “&Dgr;” will not take place. Consequently, in the trench element isolating regions
122
, the actual dimension “Wactual” can be made 0.5 &mgr;m or less.
Since the trenches
121
are formed inside the silicon substrate
101
, the trench element isolating regions
122
can be formed deep in the substrate
101
. This enables the trench element isolating regions to be made thicker than the LOCOS element isolating regions
102
.
The trench element isolating method has realized thick element isolating regions
122
even in a memory cell array where microscopic line patterns are repeated. This w

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