Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2001-08-09
2002-11-05
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S185160, C365S185170
Reexamination Certificate
active
06477089
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory and, more particularly, to a nonvolatile semiconductor memory circuit capable of reading data at high speed.
Japanese Unexamined Patent Publication No. 61-180999. and Japanese Unexamined Patent Publication No. 61-181000 have disclosed technologies related to erasable programmable read only memories (EPROM's) exemplifying conventional nonvolatile semiconductor memories.
As described in the aforesaid literature, EPROM's are classified into a type having NOR memory cells and another type having NAND memory cells. The NOR memory cells are advantageous if the speed for reading data is important; however, the NOR memory cells is disadvantageous in that it requires a larger layout area, as compared with the NAND memory cells. For this reason, there are cases where an X-cell system as an extension of a NOR memory cell layout system is used in order to reduce the layout area of memory cells.
According to the X cell system, each source of a pair of memory cells that is selected on the basis of the same row address is connected to a column line. The drains of the pair of memory cells are respectively connected to the two it lines adjacent to the column line. The paired memory cells are simultaneously selected, requiring at least two data buses.
The EPROM employing the X cell system has a memory cell block wherein memory cells for storing data are disposed in a matrix pattern. The memory cell block is provided with a plurality of bit lines and column lines that are alternately disposed, and a plurality of row lines that are orthogonal thereto. A memory cell composed of a MOS transistor is provided between each bit line and each column line.
A row address decoder for selecting one from among the plural row lines is connected to the plural row lines. One end of the bit lines and the column lines is provided with a bias circuit for setting the potentials thereof at predetermined levels. Furthermore, a column switch that is controlled by the column address decoder and selects one set of either the bit lines or the column lines is connected to the other end of the bit lines and the column lines. The bit lines and the data buses are connected via the column switch. A detecting circuit for outputting a voltage based on a current passing through a bit line is connected to each data bus.
According to the conventional EPROM, however, a bit line that has not been selected by the column address decoder (non-selected bit line) is charged to an output voltage level of a bias circuit, i.e., a cell bias voltage level, by a memory cell other than a selected memory cell belonging to the same row address as that of the memory cell which has been selected (a selected memory cell). As a result, as shown in
FIG. 16
, the voltage of a selected bit line changes from the cell bias voltage to a sense voltage of the detecting circuit over a certain time after a column address is changed.
In addition, the drain line of a memory cell disconnected from the bias circuit turns into a so-called floating node. Therefore, a bit line does not necessarily retain a cell bias voltage immediately after it is selected, because of a non-selected cell current, junction leakage, or the like.
Thus, according to the conventional EPROM, it has been necessary to wait until the drain line of a memory cell connected to the bias circuit settles to the cell bias voltage, and the voltage of a bit line settles to the sense voltage of the detecting circuit, as shown in
FIG. 16
, before the bit line is changed to read data. This waiting time has been partly responsible for interfering with achieving higher speed in reading data.
SUMMARY OF THE INVENTION
The present invention has been made with a view toward solving the problem described above, and it is an object of the present invention to provide a nonvolatile semiconductor memory capable of reading data at higher speed.
A nonvolatile semiconductor memory of the present invention comprises a cell bias circuit supplying a first voltage, a memory cell array having memory cell transistors, word lines, drain lines disposed perpendicular to the word lines and source lines disposed perpendicular to the word lines. The nonvolatile semiconductor memory further comprises source line equalizing transistors connected between the cell bias circuit and the source lines, respectively, the source line equalizing transistors turning on during a stand by mode, drain line equalizing transistors connected between the cell bias circuit and the drain lines, respectively,. the drain line equalizing transistors turning on during the stand by mode, bit lines, main source lines, source line selecting transistors connected between the main source lines and the source lines, respectively, the source line selecting transistors turning off during the stand by mode, drain line selecting transistors connected between the bit lines and the drain lines, respectively, the drain line selecting transistors turning off during the stand by mode and a detecting circuit connected to said bit lines for supplying the first voltage to the bit lines for detecting data stored in the memory cells.
REFERENCES:
patent: 5450354 (1995-09-01), Sawada et al.
patent: 5517448 (1996-05-01), Liu
patent: 5748538 (1998-05-01), Lee et al.
patent: 5886937 (1999-03-01), Jang
patent: 6044033 (2000-03-01), Jang
patent: 6147912 (2000-11-01), Kitazawa
patent: 6278649 (2001-08-01), Lee et al.
patent: 6324109 (2001-11-01), Inoue
patent: 61-181000 (1986-08-01), None
patent: 2-210694 (1990-08-01), None
patent: 6-318683 (1994-11-01), None
patent: 61-180999 (1996-08-01), None
Harada Teruhiro
Takeda Keiichiro
Elms Richard
Nguyen Tuan T.
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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