Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2001-01-04
2002-11-05
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S344000
Reexamination Certificate
active
06476647
ABSTRACT:
The invention relates to an improved method and circuit arrangement for signal processing. The invention finds particular utility in the processing of analog signals in applications where low energy consumption is of the essence. Signal processing in the present context refers to addition subtraction, integration or differentiation of voltages or, for that matter, charges or currents, that represent signals.
BACKGROUND OF THE INVENTION
Processing analog signals often involves the problem of how to achieve low energy consumption as the continuous current consumption of linearly operating active analog circuits, such as e.g. operational amplifiers, is considerable.
Basic methods are known from the prior art wherein the processing of signal samples may be performed by processing the signal by means of a switching transistor that only transfers charge impulses, instead of using structures that continuously consume current. Such methods are disclosed in patent documents FI 89838 (corresponding to EP 473,436 and U.S. Pat. No. 5,387,874), FI 931831 (corresponding to EP 621,550 and U.S. Pat. No. 5,497,116) and Finnish patent document FI 101914.
Patent document FI 89838 discloses an integrating circuit wherein switches are used to control the storing in a sampling capacitor of charge samples taken from a signal voltage, and the discharging of charge samples from the sampling capacitor into an integrating capacitor. The circuit disclosed substantially consumes current only while charges are being transferred. The arrangement, however, has the drawback that it requires separate switch arrangements for the positive and negative cycles of the signal voltage as well as separate clock stages to control the switches, thus making the circuit complicated. Moreover, the use of separate circuit elements for the processing of the signal's negative and positive cycles may result in signal distortion caused by threshold voltages and component variation.
The drawbacks of the circuit described above can be avoided by using the arrangement disclosed in patent document FI 931831. To aid in understanding the operation of the present invention and its advantages over the prior art, the operation of the circuit arrangement disclosed in said document is described below in detail with reference to
FIGS. 1
to
5
.
FIG. 1
shows a signal processing circuit implemented with transistors T
1
and T
2
, in which circuit the end result is a time-discrete integral of voltage (U
S
−U
Ref
). Transistors T
1
, T
2
are N-type MOS transistors, or N-MOS transistors. Switches S
21
to S
30
in the circuit shown in
FIG. 1
are controlled by clock signals
1
to
4
. The clock signals
1
to
4
control the switches in four successive stages such that e.g. during clock stage
1
clock signal
1
sets the switches controlled by clock signal
1
into conductive state. Switches are below denoted using the letter S and indices such that the subscript refers to the switch number, which is running, and the superscript refers to the clock stages during which the switch is conductive. For example, marking S
21
1.3
refers to switch
21
which is conductive during clock stages
1
and
3
, controlled by clock signals
1
and
4
. During the other clock stages
2
and
4
the switch is non-conductive. Similarly, a denotation of voltage provided with a superscript refers to the voltage appearing during the clock stage indicated by the superscript, and a denotation of charge provided with a superscript refers to the charge appearing or transferred during the clock stage indicated by the superscript. Thus, U
Ci
2
refers to the voltage U of capacitance Ci during/at the end of clock stage
2
. The clock pulses are so-called non-overlapping clock pulses, i.e. during a given stage only the switches intended to be closed during said stage are conductive, and the other switches are open.
The operation of the clock stages
1
to
4
in the circuit is described in detail in
FIGS. 2
to
5
, showing only those elements of the circuit of
FIG. 1
that are essential from the point of view of the operation of the clock stage in question. The signs (i.e. polarities, e.g. positive or negative) of the signals and voltages are indicated relative to the ground potential.
FIG. 2
illustrates the operation during clock stage
1
. Switches S
21
, S
22
, S
23
and S
24
are closed during clock stage
1
so that the charge-transferring capacitor C
i
, here also called sampling capacitor C
i
, is charged up to voltage U
ci
1
:
U
Ci
1
=
U
S
1
+
U
Ref
+
U
th1
(
1
)
where U
th1
is the threshold voltage of the gate-source voltage of transistor T
1
. When the gain of transistor T
1
is large, the charge transferred to the sampling capacitor C
i
comes substantially from the circuit's supply voltage VDD and not from the signal voltage U
S
.
The operation during the subsequent clock stage
2
is illustrated in FIG.
3
. During clock stage
2
, switches S
26
, S
27
and S
28
are conductive (closed) so that the sampling capacitor C
i
supplies gate-source voltage to transistor T
2
, facilitating flow of current from the positive operating voltage VDD to the integrating capacitor C
O
. The current flow continues until the sampling capacitor C
i
has discharged down to the threshold voltage U
th2
of the gate-source junction of transistor T
2
, at which point the current flow stops. So, charge is transferred from the sampling capacitor C
i
to the integrating capacitor C
O
until the voltage of capacitor C
i
has dropped to U
th2
. Thus, during clock stage
2
, a charge is transferred from the charge-transferring capacitor C
i
to the integrating capacitor C
O
according to the equation:
&Dgr;
Q
2
=C
1
(
U
S
+U
Ref
−U
th1
−U
th2
) (2)
FIG. 4
illustrates the operation of the circuit during clock stage
3
when switches S
21
, S
23
, S
24
and S
25
are closed. The sampling capacitor C
i
is connected to the reference voltage U
Ref
via transistor T
1
so that capacitor C
i
is charged up to voltage
U
Ci
3
=U
Ref
−U
th1
(3)
FIG. 5
illustrates the operation of the circuit during the last clock stage
4
when switches S
26
, S
29
and S
30
are closed. The sampling capacitor C
i
supplies gate-source voltage to transistor T
2
facilitating flow of current through the sampling capacitor C
i
from the integrating capacitor C
O
to the lower operating voltage VSS. The current flow continues until the sampling capacitor C
i
has discharged down to the threshold voltage U
th2
of the gate-source junction of transistor T
2
. The negative charge transferred to the integrating capacitor C
O
is then
&Dgr;Q
4
=−C
1
(
U
Ref
−U
th1
−U
th2
) (4)
When the gain of transistor T
2
is large, as it is in a good bipolar transistor, or near infinite, as it is in a field-effect transistor (e.g. MOS transistor), also the charge transferred at the charge transfer stages comes from the supply voltage (VDD, VSS) and has substantially that precise magnitude which is required to transfer the desired charge from the sampling capacitance C
i
to the integrating capacitance C
O
. The charge transferred during all clock stages
1
to
4
to the output of the circuit at the integrating capacitor C
O
, totals in the sum of equations (2) and (4), i.e.
&Dgr;Q
tot
=C
1
(
U
s
+U
Ref
−U
ref
)=
C
i
U
S
(5)
Accordingly, during one cycle Tr of clock stages, i.e. during clock stages
1
to
4
, the voltage of the integrating capacitor C
O
changes value according to equation (6):
Δ
U
C
o
=
C
i
C
o
(
U
s
+
U
Ref
-
U
Ref
)
=
C
i
C
o
U
s
(
6
)
Thus, the circuit shown in
FIG. 1
becomes a discrete-time, positive signal voltage integrating circuit the time integration weight coefficient of which is C
i
/C
O
. The sign of the integration can be changed to negative by interchanging the order of performance of the aforementioned clock stages
2
and
4
, so that the operation according to clock stage
4
is performed after sta
Nokia Mobile Phones Ltd.
Perman & Green LLP
Tran Toan
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