Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-10-03
2006-10-03
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000, C438S589000
Reexamination Certificate
active
07115474
ABSTRACT:
A trench region14is formed in a memory cell P-type well13. Two NAND-type memory cell units ND1and ND2are respectively formed along both side wall portions of this trench region14.A floating gate FG and a control gate CG in these NAND-type memory cell units ND1and ND2are formed self-aligningly without using memory cell units ND1and ND2is formed via an interlayer dielectric30. The bit line pitch of this bit line BL is set at 2 F. Hence, the size of a nonvolatile semiconductor memory can be reduced.
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Sakui Koji
Watanabe Toshiharu
Kabushiki Kaisha Toshiba
Thomas Toniae M.
Wilczewski Mary
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