Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-30
2001-10-16
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S593000
Reexamination Certificate
active
06303440
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field Related to the Invention
The present invention concerns a method for manufacturing a semiconductor, in particular a method for manufacturing a two-layered structure of a nonvolatile semiconductor memory.
2. Description of the Related Art
In the memory cell array of the nonvolatile semiconductor memory, there is a structure which contains the two-layered gate structure comprising a floating gate, which is electrically insulated from the periphery, in addition to a control gate of a usual gate.
The structure of the nonvolatile memory, which includes the conventional two-layered structure, is described in FIG.
1
.
Cell gate oxide film
83
(about 100 angstrom thick) is formed on the surface within the region enclosed by field oxide film
82
, which is formed on semiconductor substrate
81
, while floating gate
84
(about 1000 angstrom to 2000 angstrom thick) is formed on cell gate oxide film
83
. On the further upper side, for example, control gate
86
of polysilicon WSi 2000 angstrom/1200 angstrom is formed by ONO (oxide
itride/oxide) insulation film
85
containing a three layer structure, such a as silicone oxide film/silicone nitride layer/silicone oxide layer of 50~60 angstrom/60 angstrom/50~60 angstrom, respectively, which form the MOS transistor.
When electrons are involved in floating gate
84
, the channel cannot be easily induced by the negative charge of electrons, even if a word line attains a high voltage, where the threshold voltage rises too high to turn on. When electrons are not involved in floating gate
84
, a high voltage is applied to control gate
86
to turn on this transistor, if the word line attains a high voltage, where this transistor is turned on.
On the other hand, electrons can be accumulated in floating gate
84
, by regulating the voltage to apply to control gate
86
and a drain region (not depicted in the Figures).
Floating gate
84
is formed by diffusing an N type impurity, for instance, phosphorus, to attain a uniform density after deposition of polysilicon.
Meanwhile, a bottom oxide film, a silicon oxide film of the lowest layer for ONO insulating film
85
, is formed by oxidizing polysilicon by thermal oxidation, where the impurity pertaining to floating gate
84
is diffused. This oxidation should proceed at the high temperature of about 850~1000 C. in order to obtain sufficient insulation characteristics and charge storage characteristics. This process uses ONO insulating film
85
in three layers, which have, for instance, enhanced charge storage characteristics, rather than formation with the single silicon oxide film layer only.
However, when the memory cell is formed using the above-mentioned method, phosphorus within floating gate
84
is diffused into the cell gate oxide film through the route shown in
FIG. 1
in the course of the oxidation process for the bottom oxide film, which results in structural damage within the cell gate oxide film. Moreover, it invokes a problem concerning reliability with an increase in the leak current.
Furthermore, because floating gate
84
is formed through the route indicated by arrow
2
in
FIG. 1
, phosphorus in polysilicon is involved in the bottom oxide film during oxidation of polysilicon, which results in degradation in the bottom oxide film quality.
Also, the oxidation rate for polysilicon containing abundant phosphorus is quickened by, that is, accelerating phenomena, which invokes a problem in the film thickness controllability. Moreover, it makes it difficult to form the desired oxide film in the desired thin film.
In the preprocess used in forming the bottom oxide film, a polysilicon surface containing phosphorus is flooded with some liquid during a chemical process, e.g. wafer cleaning process, or exposed an atmosphere, which brings up oxidation, while a rough natural oxide film will be formed. In such a thick region, where the bottom oxide film thickness exceeds 10 nm, the influence of the above-mentioned natural oxide film can be ignored. However, when the bottom oxidation film thickness must be minimized to less than 10 nm, corresponding to micronization of devices, any incorrect quality natural oxidation film, 2 to 3 nm thick, cannot be ignored, where countermeasures must be taken.
The natural oxide film had been formed before the oxide film deposition, even with the LP-CVD (Low pressure-Chemical Vapor Deposition) chamber of about 700° C., usually when the bottom oxide film was formed by the LP-CVD method.
These natural oxide films have changed the film quality and the film thickness according to exposure time and process conditions of the wafer, which deteriorates the film thickness and the film quality control of the bottom oxide film.
In addition, the natural oxide film is incorrect in regard to the film quality, which results in degradation of the bottom oxide resulting in wrong film quality, often represented in insulation resistance, etc.
As mentioned above, there is a problem wherein the degradation in the cell gate oxide film quality occurs due to the affects of phosphorus in the floating gate in a conventional invention, which results in reliability degradation, and the controllability of the bottom oxide film cannot be improved to achieve excellent film quality with thin film thickness.
SUMMARY OF THE INVENTION
It is an object of the present invention to prevent any damage to the call gate oxide film, and to provide a method for manufacturing a nonvolatile semiconductor memory to form a bottom oxide film which is excellent in film quality.
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Wolf et al., “Silicon Processing for the VLSI Era vol. 1: Process Technology”, Lattice Press, pp. 164-169 (1986).
Araki Yoshiko
Mori Seiichi
Booth Richard
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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