Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-06-25
2000-06-27
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438585, H01L 21336, H01L 213205, H01L 214763
Patent
active
060806249
ABSTRACT:
The present invention is directed to a flash EEPROM in which a plurality of resist patterns are arranged like an island such that only an interlayer insulation film formed on a field oxide film is left in order to insulate drain diffusion layers of cell transistors in the row direction from each other when contacts of a memory cell group are subjected to PEP. Using the island-like resist patterns as masks, contact holes communicating with both the drain diffusion layers and source diffusion layers are made. Since, therefore, drain and source contact holes are arranged in matrix, the PEP margin can greatly be increased, thereby making it possible to prevent the problems of forming no contact holes and causing a short circuit between the gate and contact from arising.
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Aritome Seiichi
Kamiya Eiji
Kabushiki Kaisha Toshiba
Lindsay Jr. Walter L.
Niebling John F.
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