Nonvolatile semiconductor memory and manufacturing method...

Details Nonvolatile semiconductor memory and manufacturing method... Nonvolatile semiconductor memory and manufacturing method...

2006-10-17

2006-10-17

Tran, Long (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S201000, C257SE21691, C257SE21685

Reexamination Certificate

active

07122430

ABSTRACT:
The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.

REFERENCES:
patent: 2001/0018274 (2001-08-01), Sugizaki et al.
patent: 2003/0183883 (2003-10-01), Shimizu et al.
patent: 2005/0141291 (2005-06-01), Noguchi et al.
patent: 9-82925 (1997-03-01), None
patent: 2001-15617 (2001-01-01), None
patent: 2001-168306 (2001-06-01), None
patent: 2001-210809 (2001-08-01), None
patent: 2003-37251 (2003-02-01), None

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