Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-08-09
2005-08-09
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S589000
Reexamination Certificate
active
06927139
ABSTRACT:
A semiconductor memory encompasses a memory cell matrix, which embraces device isolation films running along the column-direction, arranged alternatively between the cell columns; first conductive layers having top surfaces lower than the device isolation films; inter-electrode dielectrics arranged on the corresponding first conductive layers, the inter-electrode dielectric has a dielectric constant larger than that of silicon oxide; and second conductive layers running along the row-direction, each of the second conductive layers arranged on the inter-electrode dielectric and the device isolation films so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.
REFERENCES:
patent: 5578516 (1996-11-01), Chou
patent: 5792689 (1998-08-01), Yang et al.
patent: 2001-15616 (2001-01-01), None
Mizushima Ichiro
Ozawa Yoshio
Sato Atsuhiro
Tanaka Masayuki
Yamashita Hiroki
Dang Phuc T.
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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