Nonvolatile phase change memory device and biasing method...

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

Reexamination Certificate

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C365S185180, C365S190000

Reexamination Certificate

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11195359

ABSTRACT:
A nonvolatile phase change memory device including a memory array formed by memory cells arranged in rows and columns, word lines connected to first terminals of memory cells arranged on the same row, and bit lines connected to second terminals of memory cells arranged on the same column; a row decoder coupled to the memory array to bias the word lines; a column decoder coupled to the memory array to bias the bit lines; and a biasing circuit coupled to the row decoder and to the column decoder to supply a first biasing voltage and a second biasing voltage to the terminals of an addressed memory cell, wherein the first biasing voltage is a positive biasing voltage and the second biasing voltage is a negative biasing voltage.

REFERENCES:
patent: 5931563 (1999-08-01), Jinbo
patent: 6072722 (2000-06-01), Hirano
patent: 6753561 (2004-06-01), Rinerson et al.
patent: 2002/0089869 (2002-07-01), Hogan
patent: 2003/0002338 (2003-01-01), Xu et al.
patent: 2003/0123284 (2003-07-01), Lowrey et al.
patent: 2006/0002173 (2006-01-01), Parkinson et al.

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