Nonvolatile memory with pedestals

Details Nonvolatile memory with pedestals Nonvolatile memory with pedestals

2003-03-28

2004-09-07

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S319000

Reexamination Certificate

active

06787415

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to integrated circuits, and more particularly to nonvolatile memories.
In a typical integrated circuit, a number of conductive or semiconductor layers are separated by dielectric layers. The conductive and semiconductor layers contact each other through openings in the dielectric layers. It is desirable to facilitate the formation of these contact openings in the dielectric layers.
SUMMARY
This section summarizes some features of the invention. Other features are described in subsequent sections. The invention is defined by the appended claims.
Formation of contact openings is particularly difficult if an underlying feature is narrow or sloped. See for example K. Naruke et al., “A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on Its Source Side”, IEDM Technical Digest 1989, pages 603-606, hereby incorporated by reference. The Naruke article describes a flash memory with a select gate formed as a sidewall spacer. The spacer is formed over a sidewall of a structure containing the floating and control gates. The spacer is formed by depositing and anisotropically etching a polysilicon layer. The spacer can be quite narrow. Also, it is well known that sidewall spacers formed by an anisotropic etch without a mask may have a sloping surface, their height gradually decreasing to zero. When a contact opening is formed to a narrow spacer, the photolithographic alignment must be precise. Also, the contact resistance can be high. Further, due to the sloping surface, the etch of the contact opening must be highly selective to the spacer material because the loss of the spacer material may further reduce the spacer width (making the spacer even more narrow).
In some embodiments of the present invention, formation of contacts to spacers is facilitated by use of pedestals in the area of the contact openings. A pedestal is an upward projecting feature, possibly a dummy feature having no electrical functionality. For example, in the case of the memory described in the Naruke article cited above, a pedestal can be provided near the sidewall of the structure containing the floating and control gates. The pedestal is formed before the spacer layer (the polysilicon layer) is deposited. When the spacer layer is deposited, the spacer layer fills the area between the pedestal and the structure with the floating and control gates. The minimum thickness of the select gate is therefore increased near the pedestal. The increased thickness counteracts the loss of the select gate material during the etch of the contact opening. Consequently, the etch process margin is increased (the etch does not have to be as selective, or as carefully timed, to avoid the loss of the select gate material), the photolithographic alignment tolerance can be relaxed when the opening is being patterned, and the contact resistance tends to be lower. In addition, the top surface of the select gate becomes less sloped. Further, the top surface becomes higher, so the contact opening does not have to be as deep.
In some embodiments, the pedestal has sub-lithographic dimensions because it does not have to be printed reliably when it is photolithographically patterned. The pedestal may be formed from the same layer or layers as other features of the integrated circuit.
The invention is not limited to spacers, select gates, polysilicon, and other particulars. The invention is defined by the appended claims.


REFERENCES:
patent: 6355524 (2002-03-01), Tuan et al.
patent: 6403417 (2002-06-01), Chien et al.
patent: 6451708 (2002-09-01), Ha
Naruke, K.; Yamada, S.; Obi, E.; Taguchi, S.; and Wada, M. “A New Flash-Erase EEPROM Cell with A Sidewall Select-Gate On Its Source Side,” 1989 IEEE, pp. 604-606.
Wu, A.T.; Chan T.Y.; Ko, P.K.; and Hu, C. “A Novel High-Speed, 5-Volt Programming EPROM Structure With Source-Side Injection,” 1986 IEEE, 584-587.
Mizutani, Yoshihisa; and Makita, Koji “A New EPROM Cell With A Sidewall Floating Gate Fro High-Density and High Performance Device,” 1985 IEEE, 635-638.
Ma, Y.; Pang, C.S.; Pathak, J.; Tsao, S.C.; Chang, C.F.; Yamauchi, Y.; Yoshimi, M. “A Novel High Density Contactless Flash Memory Array Using Split-Gate Source-Side-Injection Cell for 5V-Only Applications,” 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 49-50.
Mih, Rebecca et al. “0.18um Modular Triple Self-Aligned Embedded Split-Gate Flash Memory,” 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 120-121.

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