Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2008-02-26
2009-12-29
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S185080
Reexamination Certificate
active
07639546
ABSTRACT:
A nonvolatile semiconductor memory device includes a latch circuit having two nodes, a nonvolatile memory cell including two MIS transistors, a bit swapping unit configured to provide straight connections between the two nodes and the two MIS transistors during a first operation mode and to provide cross connections between the two nodes and the two MIS transistors during a second operation mode, and a control circuit configured to cause, in one of the first and second operation modes, the nonvolatile memory cell to store the data latched in the latch circuit as an irreversible change of transistor characteristics occurring in a selected one of the two MIS transistors, and further configured to cause, in another one of the first and second operation modes, the latch circuit to detect the data stored in the nonvolatile memory cell.
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Kikuchi Takashi
Noda Kenji
Ladas & Parry LLP
Nguyen Tan T.
Nscore Inc.
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