Nonvolatile memory structures and fabrication methods

Details Nonvolatile memory structures and fabrication methods Nonvolatile memory structures and fabrication methods

2000-08-15

2002-03-12

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06355524

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor technology, and more particularly to nonvolatile memories.
FIGS. 1-8
illustrate fabrication of a conventional nonvolatile stacked-gate flash memory described in U.S. Pat. No. 6,013,551 issued Jan. 11, 2000 to J. Chen et al. Silicon oxide layer
108
(“tunnel oxide”) is grown on P-doped silicon substrate
150
. Doped polysilicon
124
is deposited over oxide
108
. Polysilicon
124
will provide floating gates for memory cell transistors.
Mask
106
is formed over the structure. Polysilicon
124
, oxide
108
, and substrate
150
are etched through the mask openings. Trenches
910
are formed in the substrate as a result (FIG.
2
).
As shown in
FIG. 3
, the structure is covered with dielectric which fills the trenches. More particularly, silicon oxide
90
is grown by thermal oxidation. Then silicon oxide
94
is deposited by PECVD (plasma enhanced chemical vapor deposition). Then thick silicon oxide layer
96
is deposited by SACVD (subatomspheric chemical vapor deposition).
The structure is subjected to chemical mechanical polishing (CMP). Polysilicon
124
becomes exposed during this step, as shown in FIG.
4
.
As shown in
FIG. 5
, ONO (silicon oxide, silicon nitride, silicon oxide) layer
98
is formed on the structure. Silicon
99
is deposited on top. Then tungsten silicide
100
is deposited.
Then a mask is formed (not shown), and the layers
100
,
99
,
98
,
124
are patterned (FIG.
6
). Layer
124
provides floating gates, and layers
99
,
100
provide control gates and wordlines.
Then mask
101
is formed over the structure, as shown in FIG.
8
. Silicon oxide etch removes those portions of oxide layers
90
,
94
,
96
which are exposed by mask
101
. After the etch, the mask remains in place, as dopant is implanted to form source lines
103
.
Other implantation steps are performed to properly dope the source and drain regions.
Alternative memory structures and fabrication methods are desirable.
SUMMARY
Some embodiments of the present invention provide a method for manufacturing an integrated circuit comprising nonvolatile memory, the method comprising:
(a) forming, over a semiconductor region S
1
, a first layer, wherein the integrated circuit is to include a plurality of nonvolatile memory cells each of which has a floating gate comprising a portion of the first layer;
(b) forming trenches in the region S
1
through openings in the first layer, and filling the trenches with insulation;
(c) forming a second layer over the region S
1
, wherein each of said cells is to have a conductive gate comprising a portion of the second layer, the conductive gate being insulated from the cell's floating gate;
(d) patterning the second layer to form strips extending in a predetermined direction, each strip crossing over a plurality of trenches;
(e) removing that portion of the first layer over the region S
1
which is not covered by the second layer, to form a plurality of first structures each of which comprises a strip made from the second layer and also comprises a portion of the first layer under the strip, each first structure having a first sidewall;
(f) forming a third layer over the first and second layers, and removing a portion of the third layer by a process comprising an anisotropic etch, to form a spacer over at least a portion of the first sidewall of each first structure, each spacer being insulated from materials of the first and second layers in the respective first structure;
(g) removing a portion of the third layer from over a portion of the region S
1
so as not to completely remove said spacers, wherein each of said cells comprises a conductive gate comprising a portion of a spacer over a first sidewall of a first structure; and
(h) introducing dopant into at least a portion of the region S
1
;
wherein the operations (g) and (h) are performed using a single photolithographic masking operation performed before the operation (g).
Some embodiments of the present invention provide a method for manufacturing an integrated circuit comprising a nonvolatile memory, the method comprising:
(a) forming insulation on a semiconductor region S
1
;
(b) forming, over the insulation, a plurality of conductive first strips of first material from which floating gates are to be formed, the first strips extending in a first direction;
(c) forming trenches in the semiconductor region S
1
, each trench extending between adjacent first strips of the first material, the trenches containing an insulator;
(d) forming insulation over the first strips;
(e) forming second material from which conductive memory gates are to be formed, wherein the second material is formed over the insulation formed over the first material;
(f) forming a mask over the second material, and patterning the second material using said mask, to form second strips of the second material, the second strips extending in a second direction at an angle to the first strips;
(g) removing that portion of the first material over the region S
1
which is not covered by the second material, to form a plurality of first structures each of which comprises a second strip of the second material and also comprises floating gates formed from the first material under the second material, each first structure having a first sidewall;
(h) forming insulation over exposed sidewalls of the floating gates and of the second material in the first structures;
(i) forming a third material over the first and second materials, and removing a portion of the third material by a process comprising an anisotropic etch, to form spacers over at least portions of the first sidewalls of each first structure;
(j) forming a mask using photolithography, the mask covering the spacers over the first sidewalls of the first structures;
(j) removing the third layer by a process comprising an etch selective to said mask, so as not to remove the spacers which are to provide conductive gates for the nonvolatile memory; and
(k) introducing dopant into the region S
1
, wherein the dopant is blocked by said mask from portions of the region S
1
.
Some embodiments of the present invention provide a method for manufacturing an integrated circuit comprising nonvolatile memory, the method comprising:
(a) forming over a semiconductor region S
1
, a first layer comprising a plurality of first strips extending in a first direction, wherein the memory is to include a plurality of nonvolatile memory cells each of which has a floating gate comprising a portion of the first layer;
(b) forming trenches in the semiconductor region S
1
, each trench extending in the first direction between adjacent first strips, the trenches containing an insulation;
(c) forming, over the first layer, a second layer, wherein each of said cells is to have a conductive gate comprising a portion of the second layer, the conductive gate being insulated from the cell's floating gate, the second layer comprising a plurality of second strips extending at an angle to the first strips;
(d) removing that portion of the first layer over the region S
1
which is not covered by the second layer, to form a plurality of first structures each of which comprises a second strip and also comprises a portion of the first layer under the second strip, each first structure having a first sidewall;
(f) forming a third layer over the first and second layers, and removing a portion of the third layer by a process comprising an anisotropic etch, to form spacers over at least portions of the first sidewalls of each first structure, each spacer being insulated from materials of the first and second layers in the respective first structure;
(g) removing the third layer so as not to remove the spacers, the spacers over the first sidewalls being to provide conductive gates for the nonvolatile memory cells;
(h) introducing dopant into at least a portion of the region S
1
;
(i) after the operation (h), removing at least a portion of the insulation from the trenches; and
(j) after the operation (i), introducing dopant into at least a por

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