Static information storage and retrieval – Read/write circuit – Including signal clamping
Reexamination Certificate
2003-01-22
2004-06-29
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including signal clamping
C365S185290, C365S189110, C365S189120, C365S226000
Reexamination Certificate
active
06757201
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile memory and a data processing device incorporating the same, specifically to a control method of the erase and write processing by applying a boosted voltage to nonvolatile memory cells, which is an effective technique for use in an IC (Integrated Circuit) card incorporating, for example, an EEPROM (Electrically Erasable and Programmable Read Only Memory) and a CPU (Central Processing Unit) and so forth.
The EEPROM is widely used together with a logical unit such as a CPU, in a microcomputer for an IC card. The nonvolatile memory cell of the EEPROM is composed of a two-transistor unit including a memory MOS transistor that takes charge of storage and a selection MOS transistor that selects the concerned memory MOS transistor and takes out the information. The memory MOS transistor often adopts the MONOS structure. The memory MOS transistor is made up with a source, drain, insulated silicon nitride film, and control gate. To attain a state in which the threshold voltage of the memory cell is programmed to a comparably high voltage, namely, the write state, it is needed to capture electrons in the silicon nitride film by applying a supply voltage (Vcc), for example, 3V to the control gate, and a high voltage (−Vpp), for example, −10V to a well region (back gate). To attain a state in which the threshold voltage of the memory cell is programmed to a comparably low voltage, namely, the erase sate, it is needed to store holes in the silicon nitride film by applying high voltage (−Vpp), for example, −10V to the control gate, and the supply voltage (Vcc), for example, 3V to the well region. In a microcomputer for an IC card and the like, a booster to generate the above high voltage is built in on one chip, so that operational power supplies are unified into a single supply voltage.
In order to evaluate the performance of an electrically erasable and rewritable nonvolatile memory, the rewritable frequency and the data retention characteristic are used as the indicator of performance. The characteristic deterioration of the silicon nitride film and so forth due to repeated applications of the high voltage gives a limitation to the rewritable frequency. As the applications thereat of the high voltage become more precipitous, the electric stresses become severer, which further advances the characteristic deterioration, so that the rewritable frequency becomes still lower. On the other hand, as the application time of the high voltage in the erase and write processing becomes longer, the amount of electrons and holes to be captured becomes increased; accordingly, the data retention characteristic (characteristic of time during which data are held stably without mutations) becomes improved.
Therefore, in order to achieve a satisfactory rewritable frequency and better data retention characteristic, it is necessary to comparably slow the boosting speed of applying the high voltage and to comparably elongate the application time of the high voltage.
SUMMARY OF THE INVENTION
The inventor examined the measures to counter the application program described in the programming language such as the JAVA (registered trademark) or the like (hereunder, simply referred to as virtual machine program), where it was found that the shortening of the rewrite time to the EEPROM was very important. It is necessary to frequently rewrite multiple variables in the execution of the virtual machine program; here, the inventor considered that it would become necessary to appropriate the EEPROM to the temporary areas for manipulating the variables, in such an environment that cannot afford to plentifully use RAMs (Random Access Memory) as the work areas. The inventor further discovered that the use of the nonvolatile memory represented by the EEPROM as the temporary areas retains temporary information as it is even when the power supply is unexpectedly cut off to enable restarting the processing without requesting the host machine to resend necessary information.
The applicant of this invention has already applied for PCT/JP00/05860, which is not yet disclosed internationally. This application discloses the technique that controls the boosting speed of a booster in rewriting an EEPROM. Focusing on the erase processing, it is only needed to apply the high voltage (−Vpp) such as −10 Volts to the control gate of the memory cell to be erased, however the high voltage (−Vpp) for the memory cell to be erased is to be applied to the well region of the memory cells not to be erased that share the control gate line. Since the capacitances of the control gate and the well region are considerably different, provided that the number of bits to be written in parallel is different, the number of memory cells to be erased in parallel, which is executed beforehand, is also different; and accordingly, the driven load of the booster that supplies the high voltage is to vary. Such a change of the driven load leads to a change of the boosting speed, and produces a difference of voltage stresses to be given to the memory cells; inconsequence, significant electric stresses are accumulated in a part of the memory cells, and the rewritable frequency is anticipated to become abnormally insignificant. Accordingly, the above application by the applicant is to vary the frequency of the synchronous clock signal for the boosting operation in the booster according to the magnitude of the driven load, in a manner that the speed in the boosting operation becomes constant even if the number of memory cells to be erased in parallel varies.
An object of the present invention is to provide a technique relating to the nonvolatile memory to easily meet the mode of use that finds precedence in fast rewrite to the nonvolatile memory, and the mode of use that finds precedence in the data retention characteristic.
Another object of the invention is to provide a technique relating to the nonvolatile memory to easily meet the mode of use that finds precedence in frequent rewrite to the nonvolatile memory and data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic.
The foregoing and other objects and the novel features of the invention will become apparent from the descriptions of this specification and the appended drawings thereof.
The typical disclosures of the invention will be summarized in brief as follows.
[1] According to one aspect of the invention, the nonvolatile memory is made capable of an information storage operation to nonvolatile memory cells by the erase and write processing through a boosted voltage applied to the nonvolatile memory cells and clamping of the boosted voltage, and includes a control means for the information storage operation. The control means is able to select a first information storage operation that requires a first time, and a second information storage operation that requires a second time shorter than the first time.
In the mode of use that finds precedence in fast rewrite to the nonvolatile memory, or the mode of use that finds precedence in frequent rewrite to the nonvolatile memory and data retention during the power supply being cut off, the control means selects the second information storage operation. In the mode of use that finds precedence in the data retention characteristic, the control means selects the first information storage operation.
Many cases find that the influence to the data retention characteristic by the erase and write processing is different. When the influence to the data retention characteristic is less in the erase processing time, it is more favorable in terms of reliability to gain the difference of the first time and second time by the time difference of the erase processing. When the influence to the data retention characteristic is less in the write processing time, it is needed to gain the difference of the first time and second time by the time difference of the write processing.
The
Kato Minoru
Kon Takeo
Matsuda Yuki
Otani Kenya
Dinh Son T.
Miles & Stockbridge P.C.
Renesas Technology Corporation
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