Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-01-04
2005-01-04
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C438S258000, C438S266000
Reexamination Certificate
active
06838342
ABSTRACT:
A floating gate of a nonvolatile memory cell is formed from two conductive layers (410.1, 410.2). A dielectric (210) in substrate isolation regions and the first of the two conductive layers providing the floating gates (410.1) are formed so that the dielectric has an exposed sidewall. At least the top portion of the sidewall is exposed. Then some of the dielectric is removed from the exposed portions of the dielectric sidewalls to laterally recess the sidewalls. Then the second conductive layer (410.2) for the floating gates is formed. The recessed sidewalls of the dielectric allow the second conductive layer to expand laterally, thus increasing the capacitive coupling between the floating and control gates and improving the gate coupling ratio.
REFERENCES:
patent: 5940717 (1999-08-01), Rengarajan et al.
patent: 6127215 (2000-10-01), Joachim et al.
patent: 6130129 (2000-10-01), Chen
patent: 6200856 (2001-03-01), Chem
patent: 6222225 (2001-04-01), Nakamura et al.
patent: 6228713 (2001-05-01), Pradeep et al.
patent: 6312989 (2001-11-01), Hsieh et al.
patent: 6319794 (2001-11-01), Akatsu et al.
patent: 6323085 (2001-11-01), Sandhu et al.
patent: 6355524 (2002-03-01), Tuan et al.
patent: 6376877 (2002-04-01), Yu et al.
patent: 6417047 (2002-07-01), Isobe
patent: 6448606 (2002-09-01), Yu et al.
patent: 6518618 (2003-02-01), Fazio et al.
patent: 6555427 (2003-04-01), Shimizu
patent: 6570215 (2003-05-01), Tuan et al.
patent: 6670243 (2003-12-01), Saito
patent: 6743675 (2004-06-01), Ding
patent: 2000-174242 (2000-06-01), None
Aritome, S. et al., “A 0.67um2Self-Aligned Shallow Trench Isolation Cell (SA-STI Cell) For 3V-only 256Mbit NAND EEPROMs,” International Electron Devices meeting 1994, San Francisco, CA, Dec. 11-14, 1994, pp. 94-61—94-64.
Keeney, Stephen N., A 130nm Generation High Density Etox™ Flash Memory Technology, Intel, Corporation, Santa Clara, California, USA, 42 sheets.
U.S. Appl. No. 10/266,378 entitled “Floating Gate Memory Structures And Fabrication Methods,” filed on Oct. 7, 2002, Inventor: Chia-Shun Hsiao, Attorney Docket No. M-12200 US.
U.S. Appl. No. 10/262,785, entitled “Floating Gate Memory Fabrication Methods Comprising A Field Dielectric Etch With A Horizontal Etch Component,” filed on Oct. 1, 2002, Inventor: Yi Ding, Attorney Docket No.: M-12841 US.
Silicon, Flash and Other Non-Volatile Memory Technologies, http://www.intel.com/research/silicon/flash.htm, Sep. 12, 2002, pp. 1-4.
Patent Abstracts of Japan of JP 2000-174242.
MacPherson Kwok & Chen & Heid LLP
Picardat Kevin M.
ProMOS Technologies Inc.
Shenker Michael
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