Nonvolatile memory devices with test data buffers and...

Details Nonvolatile memory devices with test data buffers and... Nonvolatile memory devices with test data buffers and...

2004-12-06

2008-11-11

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

07451366

ABSTRACT:
A memory device includes a non-volatile memory core that includes a memory cell array and a page buffer configured to store data to be programmed in the memory cell array. The device also includes a test data input buffer configured to receive test data from an external source, and control circuit that controls the non-volatile memory core and the test data input buffer. The control circuit is configured to load test data from the test data buffer to the page buffer, to program the loaded test data in the page buffer in the memory cell array, and to retain the test data in the page buffer for subsequent programming of the memory cell array. The device may further include a test data output buffer configured to receive data read from the memory cell array, and the control circuit may be operative to convey the read data from the test data output buffer to an external recipient.

REFERENCES:
patent: 5475693 (1995-12-01), Christopherson et al.
patent: 5623620 (1997-04-01), Fandrich et al.
patent: 5748939 (1998-05-01), Rozman et al.
patent: 5954828 (1999-09-01), Lin
patent: 6477674 (2002-11-01), Bates et al.
patent: 6882569 (2005-04-01), Hosono et al.
patent: 7024598 (2006-04-01), Jeong et al.
patent: 7076667 (2006-07-01), Gama et al.
patent: 2001/0017789 (2001-08-01), Noda
patent: 2001/0053092 (2001-12-01), Kosaka et al.
patent: 2002/0069381 (2002-06-01), Jeong et al.
patent: 06-058700 (1994-03-01), None
patent: 11-258314 (1999-09-01), None
patent: 2001312900 (2001-11-01), None
“MirrorBit Flash Memory Write Buffer Programming and Page Buffer Read” Application Notes AMD Publication #25539 Rev A Amendment/0 Issue date Oct. 4, 2001.
“A Dual Page Programming Scheme for High-Speed Multi-Gb-Scale NAND Flash Memories” Takeuchi et al. 2000 Symposium on VLSI Circuits Digest of Technical Papers pp. 156-157.

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