Nonvolatile memory device using resistive elements and an...

Static information storage and retrieval – Systems using particular element – Amorphous

Reexamination Certificate

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C365S148000

Reexamination Certificate

active

07808817

ABSTRACT:
A nonvolatile memory device is configured to increase the reliability of a write operation by providing a sufficiently high write current while reducing current consumption in a read operation. The nonvolatile memory device includes a memory cell array having a plurality of nonvolatile memory cells. A global bit line and a local bit line coupled to a plurality of the nonvolatile memory cells. The local bit line has first and second nodes. First and second bit line selection circuits are included where the first bit line selection circuit is coupled to the first node of the local bit line and the second bit line selection circuit is coupled to the second node of the local bit line. The first and second bit line selection circuits operate during a first period to electrically connect the local bit line to the global bit line, and only one of the first and second bit line selection circuits operates during a second period to electrically connect the local bit line to the global bit line.

REFERENCES:
patent: 7227776 (2007-06-01), Cho et al.
patent: 7423898 (2008-09-01), Tanizaki et al.
patent: 7453722 (2008-11-01), Choi et al.
patent: 2006079756 (2006-03-01), None
patent: 1020060102682 (2006-09-01), None
patent: 1020060133740 (2006-12-01), None

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